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[Qemu-devel] [PATCH v2 12/12] target-arm: A64: add support for compare a
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 12/12] target-arm: A64: add support for compare and branch imm |
Date: |
Wed, 4 Dec 2013 19:33:29 +0000 |
From: Alexander Graf <address@hidden>
This patch adds emulation for the compare and branch insns,
CBZ and CBNZ.
Signed-off-by: Alexander Graf <address@hidden>
[claudio: adapted to new decoder,
compare with immediate 0,
introduce read_cpu_reg to get the 0 extension on (!sf)]
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate-a64.c | 44 ++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index b79672b..2a5afab 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -184,6 +184,23 @@ static TCGv_i64 cpu_reg(DisasContext *s, int reg)
}
}
+/* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
+ * representing the register contents. This TCGv is an auto-freed
+ * temporary so it need not be explicitly freed, and may be modified.
+ */
+static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
+{
+ TCGv_i64 v = new_tmp_a64_zero(s);
+ if (reg != 31) {
+ if (sf) {
+ tcg_gen_mov_i64(v, cpu_X[reg]);
+ } else {
+ tcg_gen_ext32u_i64(v, cpu_X[reg]);
+ }
+ }
+ return v;
+}
+
/*
* the instruction disassembly implemented here matches
* the instruction encoding classifications in chapter 3 (C3)
@@ -209,10 +226,33 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t
insn)
gen_goto_tb(s, 0, addr);
}
-/* Compare & branch (immediate) */
+/* C3.2.1 Compare & branch (immediate)
+ * 31 30 25 24 23 5 4 0
+ * +----+-------------+----+---------------------+--------+
+ * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
+ * +----+-------------+----+---------------------+--------+
+ */
static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
{
- unsupported_encoding(s, insn);
+ unsigned int sf, op, rt;
+ uint64_t addr;
+ int label_match;
+ TCGv_i64 tcg_cmp;
+
+ sf = extract32(insn, 31, 1);
+ op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
+ rt = extract32(insn, 0, 5);
+ addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
+
+ tcg_cmp = read_cpu_reg(s, rt, sf);
+ label_match = gen_new_label();
+
+ tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
+ tcg_cmp, 0, label_match);
+
+ gen_goto_tb(s, 0, s->pc);
+ gen_set_label(label_match);
+ gen_goto_tb(s, 1, addr);
}
/* C3.2.5 Test & branch (immediate)
--
1.7.9.5
- Re: [Qemu-devel] [PATCH v2 08/12] target-arm: A64: add support for B and BL insns, (continued)
[Qemu-devel] [PATCH v2 10/12] target-arm: A64: add support for conditional branches, Peter Maydell, 2013/12/04
[Qemu-devel] [PATCH v2 11/12] target-arm: A64: add support for 'test and branch' imm, Peter Maydell, 2013/12/04
[Qemu-devel] [PATCH v2 02/12] target-arm: A64: add set_pc cpu method, Peter Maydell, 2013/12/04
[Qemu-devel] [PATCH v2 06/12] target-arm: A64: provide skeleton for a64 insn decoding, Peter Maydell, 2013/12/04
[Qemu-devel] [PATCH v2 04/12] target-arm: Support fp registers in gdb stub, Peter Maydell, 2013/12/04
[Qemu-devel] [PATCH v2 12/12] target-arm: A64: add support for compare and branch imm,
Peter Maydell <=
[Qemu-devel] [PATCH v2 01/12] target-arm: Split A64 from A32/T32 gen_intermediate_code_internal(), Peter Maydell, 2013/12/04
[Qemu-devel] [PATCH v2 03/12] target-arm: A64: provide functions for accessing FPCR and FPSR, Peter Maydell, 2013/12/04
[Qemu-devel] [PATCH v2 05/12] target-arm: A64: add stubs for a64 specific helpers, Peter Maydell, 2013/12/04