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[Qemu-devel] [PATCH v2 03/13] target-arm: A64: add support for ADR and A
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 03/13] target-arm: A64: add support for ADR and ADRP |
Date: |
Fri, 6 Dec 2013 13:19:03 +0000 |
From: Alexander Graf <address@hidden>
Add support for the instructions described in
"C3.4.6 PC-rel. addressing" (ADR and ADRP).
Signed-off-by: Alexander Graf <address@hidden>
[claudio: adapted to new decoder structure]
Signed-off-by: Claudio Fontana <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index b6cce1e..90eaf02 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -653,10 +653,31 @@ static void disas_ldst(DisasContext *s, uint32_t insn)
}
}
-/* PC-rel. addressing */
+/* C3.4.6 PC-rel. addressing
+ * 31 30 29 28 24 23 5 4 0
+ * +----+-------+-----------+-------------------+------+
+ * | op | immlo | 1 0 0 0 0 | immhi | Rd |
+ * +----+-------+-----------+-------------------+------+
+ */
static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
{
- unsupported_encoding(s, insn);
+ unsigned int page, rd;
+ uint64_t base;
+ int64_t offset;
+
+ page = extract32(insn, 31, 1);
+ /* SignExtend(immhi:immlo) -> offset */
+ offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2);
+ rd = extract32(insn, 0, 5);
+ base = s->pc - 4;
+
+ if (page) {
+ /* ADRP (page based) */
+ base &= ~0xfff;
+ offset <<= 12;
+ }
+
+ tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
}
/* Add/subtract (immediate) */
--
1.7.9.5
- [Qemu-devel] [PATCH v2 08/13] target-arm: A64: add support for 1-src RBIT insn, (continued)
- [Qemu-devel] [PATCH v2 08/13] target-arm: A64: add support for 1-src RBIT insn, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 01/13] target-arm: A64: add support for conditional select, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 04/13] target-arm: A64: add support for EXTR, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 05/13] target-arm: A64: add support for 2-src data processing and DIV, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 09/13] target-arm: A64: add support for 1-src REV insns, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 13/13] target-arm: A64: add support for logical (immediate) insns, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 11/13] host-utils: add clrsb32/64 - count leading redundant sign bits, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 12/13] target-arm: A64: add support for 1-src CLS insn, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 03/13] target-arm: A64: add support for ADR and ADRP,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 10/13] target-arm: A64: add support for bitfield insns, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 07/13] target-arm: A64: add support for 1-src data processing and CLZ, Peter Maydell, 2013/12/06