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Re: [Qemu-devel] [PATCH v2 01/13] target-arm: A64: add support for condi
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 01/13] target-arm: A64: add support for conditional select |
Date: |
Fri, 6 Dec 2013 17:24:21 +0000 |
On 6 December 2013 16:59, Richard Henderson <address@hidden> wrote:
> Sorry for missing this in the first round: For the silly corner case of Rd ==
> XZR, tcg_rd is dead after the branch.
>
> We could either move the tcg_rd assignment down into each basic block with the
> assignment to tcg_src, or simply add
>
> if (rd == 31) {
> /* silly no-op write; until we use movcond we must special-case
> this to avoid a dead temporary across basic blocks. */
> return;
> }
>
> Either solution is ok by me.
That specialcase looks simplest to me.
thanks
-- PMM
- [Qemu-devel] [PATCH v2 00/13] target-arm: A64 decoder set 2: misc logic and bit ops, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 02/13] target-arm: A64: add support for logical (shifted register), Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 06/13] target-arm: A64: add support for 2-src shift reg insns, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 08/13] target-arm: A64: add support for 1-src RBIT insn, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 01/13] target-arm: A64: add support for conditional select, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 04/13] target-arm: A64: add support for EXTR, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 05/13] target-arm: A64: add support for 2-src data processing and DIV, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 09/13] target-arm: A64: add support for 1-src REV insns, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 13/13] target-arm: A64: add support for logical (immediate) insns, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 11/13] host-utils: add clrsb32/64 - count leading redundant sign bits, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 12/13] target-arm: A64: add support for 1-src CLS insn, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 03/13] target-arm: A64: add support for ADR and ADRP, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 10/13] target-arm: A64: add support for bitfield insns, Peter Maydell, 2013/12/06
- [Qemu-devel] [PATCH v2 07/13] target-arm: A64: add support for 1-src data processing and CLZ, Peter Maydell, 2013/12/06