Re: [Qemu-devel] outlined TLB lookup on x86

[Xin Tong]

On Thu, Nov 28, 2013 at 8:12 AM, Lluís Vilanova <address@hidden> wrote:

Xin Tong writes:

> Hi LIuis
> we can probably generate vector intrinsics using the tcg, e.g. add support to
> tcg to emit vector instructions directly in code cache

There was some discussion long ago about adding vector instructions to TCG, but
I don't remember what was the conclusion.

Hi LIuis

Can you please forward me that email if it is not difficult to find. otherwise, it is ok!.

Thank you 

Xin

Also remember that using vector instructions will "emulate" a low-associativity
TLB; don't know how much better than a 1-way TLB will that be, though.

> why would a larger TLB make some operations slower, the TLB is a direct-mapped
> hash and lookup should be O(1) there. In the cputlb, the CPU_TLB_SIZE is always
> used to index into the TLB, i.e. (X & (CPU_TLB_SIZE -1)).

It would make TLB invalidations slower (e.g., see 'tlb_flush' in
"cputlb.c"). And right now QEMU performs full TLB invalidations more frequently
than the equivalent HW needs to, although I suppose that should be quantified
too.

Lluis

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