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[Qemu-devel] [PULL 34/37] target-arm: Implement ARMv8 FP VMAXNM and VMIN
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 34/37] target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions. |
Date: |
Tue, 10 Dec 2013 14:43:30 +0000 |
From: Will Newton <address@hidden>
This adds support for the ARMv8 floating point VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 25 +++++++++++++++++++++++++
target-arm/helper.h | 5 +++++
target-arm/translate.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 80 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 263dbbf..8ec4cb1 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4085,3 +4085,28 @@ float64 VFP_HELPER(muladd, d)(float64 a, float64 b,
float64 c, void *fpstp)
float_status *fpst = fpstp;
return float64_muladd(a, b, c, 0, fpst);
}
+
+/* ARMv8 VMAXNM/VMINNM */
+float32 VFP_HELPER(maxnm, s)(float32 a, float32 b, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ return float32_maxnum(a, b, fpst);
+}
+
+float64 VFP_HELPER(maxnm, d)(float64 a, float64 b, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ return float64_maxnum(a, b, fpst);
+}
+
+float32 VFP_HELPER(minnm, s)(float32 a, float32 b, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ return float32_minnum(a, b, fpst);
+}
+
+float64 VFP_HELPER(minnm, d)(float64 a, float64 b, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ return float64_minnum(a, b, fpst);
+}
diff --git a/target-arm/helper.h b/target-arm/helper.h
index cac9564..d459a39 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -132,6 +132,11 @@ DEF_HELPER_2(neon_fcvt_f32_to_f16, i32, f32, env)
DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr)
DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr)
+DEF_HELPER_3(vfp_maxnmd, f64, f64, f64, ptr)
+DEF_HELPER_3(vfp_maxnms, f32, f32, f32, ptr)
+DEF_HELPER_3(vfp_minnmd, f64, f64, f64, ptr)
+DEF_HELPER_3(vfp_minnms, f32, f32, f32, ptr)
+
DEF_HELPER_3(recps_f32, f32, f32, f32, env)
DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env)
DEF_HELPER_2(recpe_f32, f32, f32, env)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 0a22ad8..9a8069e 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2723,6 +2723,54 @@ static int handle_vsel(uint32_t insn, uint32_t rd,
uint32_t rn, uint32_t rm,
return 0;
}
+static int handle_vminmaxnm(uint32_t insn, uint32_t rd, uint32_t rn,
+ uint32_t rm, uint32_t dp)
+{
+ uint32_t vmin = extract32(insn, 6, 1);
+ TCGv_ptr fpst = get_fpstatus_ptr(0);
+
+ if (dp) {
+ TCGv_i64 frn, frm, dest;
+
+ frn = tcg_temp_new_i64();
+ frm = tcg_temp_new_i64();
+ dest = tcg_temp_new_i64();
+
+ tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn));
+ tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm));
+ if (vmin) {
+ gen_helper_vfp_minnmd(dest, frn, frm, fpst);
+ } else {
+ gen_helper_vfp_maxnmd(dest, frn, frm, fpst);
+ }
+ tcg_gen_st_f64(dest, cpu_env, vfp_reg_offset(dp, rd));
+ tcg_temp_free_i64(frn);
+ tcg_temp_free_i64(frm);
+ tcg_temp_free_i64(dest);
+ } else {
+ TCGv_i32 frn, frm, dest;
+
+ frn = tcg_temp_new_i32();
+ frm = tcg_temp_new_i32();
+ dest = tcg_temp_new_i32();
+
+ tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn));
+ tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm));
+ if (vmin) {
+ gen_helper_vfp_minnms(dest, frn, frm, fpst);
+ } else {
+ gen_helper_vfp_maxnms(dest, frn, frm, fpst);
+ }
+ tcg_gen_st_f32(dest, cpu_env, vfp_reg_offset(dp, rd));
+ tcg_temp_free_i32(frn);
+ tcg_temp_free_i32(frm);
+ tcg_temp_free_i32(dest);
+ }
+
+ tcg_temp_free_ptr(fpst);
+ return 0;
+}
+
static int disas_vfp_v8_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
{
uint32_t rd, rn, rm, dp = extract32(insn, 8, 1);
@@ -2743,6 +2791,8 @@ static int disas_vfp_v8_insn(CPUARMState *env,
DisasContext *s, uint32_t insn)
if ((insn & 0x0f800e50) == 0x0e000a00) {
return handle_vsel(insn, rd, rn, rm, dp);
+ } else if ((insn & 0x0fb00e10) == 0x0e800a00) {
+ return handle_vminmaxnm(insn, rd, rn, rm, dp);
}
return 1;
}
--
1.8.5
- [Qemu-devel] [PULL 00/37] target-arm queue, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 02/37] cpu/a9mpcore: rename timerbusdev variable, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 16/37] net/cadence_gem: Implement mac level loopback mode, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 17/37] net/cadence_gem: Update DMA rx descriptors as we process them, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 36/37] target-arm: Use new qemu_ld/st opcodes, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 33/37] softfloat: Add minNum() and maxNum() functions to softfloat., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 34/37] target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.,
Peter Maydell <=
- [Qemu-devel] [PULL 32/37] softfloat: Remove unused argument from MINMAX macro., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 31/37] target-arm: Implement ARMv8 VSEL instruction., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 24/37] net/cadence_gem: Add missing VMSTATE_END_OF_LIST, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 10/37] target-arm: Add ARMCPU field for Linux device-tree 'compatible' string, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 28/37] net/cadence_gem: Improve can_receive debug printfery, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 29/37] net/cadence_gem: Don't rx packets when no rx buffer available, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 26/37] net/cadence_gem: Fix small packet FCS stripping, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 09/37] target-arm: Provide PSCI constants to generic QEMU code, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 27/37] net/cadence_gem: Fix register w1c logic, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 11/37] target-arm: Allow secondary KVM CPUs to be booted via PSCI, Peter Maydell, 2013/12/10