Re: [Qemu-devel] [PATCH rebased for-1.8] i386: pc: align gpa<->hpa on 1GB boundary (v6)

[Michael S. Tsirkin]

On Tue, Dec 10, 2013 at 03:21:44PM -0200, Marcelo Tosatti wrote:
> On Tue, Dec 10, 2013 at 01:05:42PM -0200, Marcelo Tosatti wrote:
> > On Tue, Dec 10, 2013 at 02:18:36PM +0100, Paolo Bonzini wrote:
> > > Il 28/11/2013 11:26, Michael S. Tsirkin ha scritto:
> > > > On Mon, Nov 25, 2013 at 06:43:13PM +0100, Paolo Bonzini wrote:
> > > >> v2: condition enablement of new mapping to new machine types (Paolo)
> > > >> v3: fix changelog
> > > >> v4: rebase
> > > >> v5: ensure alignment of piecetwo on 2MB GPA (Igor)
> > > >>     do not register zero-sized piece-one    (Igor)
> > > >> v6: fix memory leak                         (Igor)
> > > >>     fix integer overflow                    (Igor)
> > > >>
> > > >> ----
> > > >>
> > > >> Align guest physical address and host physical address
> > > >> beyond guest 4GB on a 1GB boundary.
> > > >>
> > > >> Otherwise 1GB TLBs cannot be cached for the range.
> > > >>
> > > >> Signed-off-by: Marcelo Tosatti <address@hidden>
> > > >> [Reorganize code, keep same logic. - Paolo]
> > > >> Signed-off-by: Paolo Bonzini <address@hidden>
> > > >> ---
> > > > 
> > > > Applied, thanks.
> > > 
> > > As discussed offlist, I'm not sure anymore that this is the right
> > > approach to the problem.  No doubt it is very clever, in that it is
> > > absolutely transparent to the guest.  However, the non-contiguous
> > > mapping of ram_addr_t makes it more complex to associate the right NUMA
> > > policy to the ranges.
> > 
> > Please explain what is the difference, and why the complexity does not
> > exist with non-contiguous mapping of ram_addr_t.
> 
> You are right - it forces the 1GB page which contains the hole 
> to be on the same NUMA node as the tail 1GB page - otherwise 
> incorrect NUMA assignment is not possible.

What does this phrase mean?

Are we all in agreement that we want this patch, in addition to
resizing below 4g memory?

> 
> Agreed.
> 
> > > If we could make a small guset visible change, it would be simpler to
> > > always make the PCI hole 1GB in size; it is currently 256MB for i440FX
> > > and 1.25GB for q35.  We can take a look as soon as the SeaBIOS patches
> > > are in to use QEMU-built ACPI tables.
> > > 
> > > Paolo