[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH target-arm v4 10/12] arm/highbank.c: Fix MPCore peri
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v4 10/12] arm/highbank.c: Fix MPCore periphbase name |
Date: |
Tue, 10 Dec 2013 18:58:51 -0800 |
GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
code that this is the base address of the MPCore. Rename to
MPCORE_PERIPHBASE accordingly.
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
---
changed since v2: Fixed broken comment (PMM review)
hw/arm/highbank.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index cb32325..c75b425 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -28,11 +28,11 @@
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
-#define SMP_BOOT_ADDR 0x100
-#define SMP_BOOT_REG 0x40
-#define GIC_BASE_ADDR 0xfff10000
+#define SMP_BOOT_ADDR 0x100
+#define SMP_BOOT_REG 0x40
+#define MPCORE_PERIPHBASE 0xfff10000
-#define NIRQ_GIC 160
+#define NIRQ_GIC 160
/* Board init. */
@@ -55,7 +55,7 @@ static void hb_write_secondary(ARMCPU *cpu, const struct
arm_boot_info *info)
0xe1110001, /* tst r1, r1 */
0x0afffffb, /* beq <wfi> */
0xe12fff11, /* bx r1 */
- GIC_BASE_ADDR /* privbase: gic address. */
+ MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */
};
for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
smpboot[n] = tswap32(smpboot[n]);
@@ -236,7 +236,8 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum
cxmachines machine)
cpu = ARM_CPU(object_new(object_class_get_name(oc)));
- object_property_set_int(OBJECT(cpu), GIC_BASE_ADDR, "reset-cbar",
&err);
+ object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
+ &err);
if (err) {
error_report("%s", error_get_pretty(err));
exit(1);
@@ -287,7 +288,7 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum
cxmachines machine)
qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
- sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
+ sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
for (n = 0; n < smp_cpus; n++) {
sysbus_connect_irq(busdev, n, cpu_irq[n]);
}
--
1.8.5.1
- [Qemu-devel] [PATCH target-arm v4 01/12] qom: Make uintXX added properties writable, (continued)
- [Qemu-devel] [PATCH target-arm v4 01/12] qom: Make uintXX added properties writable, Peter Crosthwaite, 2013/12/10
- [Qemu-devel] [PATCH target-arm v4 02/12] qom: Add object_property_add_bool_ptr(), Peter Crosthwaite, 2013/12/10
- [Qemu-devel] [PATCH target-arm v4 03/12] target-arm/helper.c: Allow cp15.c15 dummy override, Peter Crosthwaite, 2013/12/10
- [Qemu-devel] [PATCH target-arm v4 04/12] target-arm: Define and use ARM_FEATURE_CBAR, Peter Crosthwaite, 2013/12/10
- Re: [Qemu-devel] [PATCH target-arm v4 00/12] Fix Support for ARM CBAR and reset-hivecs, Peter Crosthwaite, 2013/12/10
- [Qemu-devel] [PATCH target-arm v4 05/12] target-arm/cpu: Convert reset CBAR to a property, Peter Crosthwaite, 2013/12/10
- [Qemu-devel] [PATCH target-arm v4 06/12] arm/highbank: Use object_new() rather than cpu_arm_init(), Peter Crosthwaite, 2013/12/10
- [Qemu-devel] [PATCH target-arm v4 07/12] arm/highbank: Fix CBAR initialisation, Peter Crosthwaite, 2013/12/10
- [Qemu-devel] [PATCH target-arm v4 08/12] arm/xilinx_zynq: Use object_new() rather than cpu_arm_init(), Peter Crosthwaite, 2013/12/10
- [Qemu-devel] [PATCH target-arm v4 09/12] arm/xilinx_zynq: Implement CBAR initialisation, Peter Crosthwaite, 2013/12/10
- [Qemu-devel] [PATCH target-arm v4 10/12] arm/highbank.c: Fix MPCore periphbase name,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v4 11/12] ARM: cpu: add "reset_hivecs" property, Peter Crosthwaite, 2013/12/10
- [Qemu-devel] [PATCH target-arm v4 12/12] ARM: arm_cpu_reset: make it possible to use high vectors for reset_exc, Peter Crosthwaite, 2013/12/10