Re: [Qemu-devel] [PATCH] piix: do not reset APIC base address (0x80) on piix4_reset.

[Gal Hammer]

Michael,

True, I haven't figure it out yet, but the current status is that recover from 
sleep doesn't work.

As far as I can tell it could be either:

1. piix4_reset shouldn't be call on resume.
2. memory_region_set_enabled (called in pm_io_space_update) shouldn't use 
config[0x80].
3. the config[0x80] shouldn't be zero in piix4_reset (current solution).
4. something else?

I'm not well familiar with the PIIX4 emulation and your help will be 
appreciated.

Thanks,

    Gal.

----- Original Message -----
From: "Michael S. Tsirkin" <address@hidden>
To: "Paolo Bonzini" <address@hidden>
Cc: "Gal Hammer" <address@hidden>, address@hidden, address@hidden
Sent: Wednesday, December 11, 2013 12:44:37 PM
Subject: Re: [PATCH] piix: do not reset APIC base address (0x80) on piix4_reset.

On Wed, Dec 11, 2013 at 11:23:27AM +0100, Paolo Bonzini wrote:
> Il 11/12/2013 10:21, Gal Hammer ha scritto:
> > Fix a bug that was introduced in commit c046e8c4. QEMU fails to
> > resume from suspend mode (S3).
> > 
> > Signed-off-by: Gal Hammer <address@hidden>
> > ---
> >  hw/acpi/piix4.c | 1 -
> >  1 file changed, 1 deletion(-)
> > 
> > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> > index 93849c8..5c736a4 100644
> > --- a/hw/acpi/piix4.c
> > +++ b/hw/acpi/piix4.c
> > @@ -376,7 +376,6 @@ static void piix4_reset(void *opaque)
> >      pci_conf[0x5b] = 0;
> >  
> >      pci_conf[0x40] = 0x01; /* PM io base read only bit */
> > -    pci_conf[0x80] = 0;
> >  
> >      if (s->kvm_enabled) {
> >          /* Mark SMM as already inited (until KVM supports SMM). */
> > 
> 
> Cc: address@hidden

It's good to know this helps but I don't think we can apply
it as is without figuring out why,
otherwise it might break something else.

-- 
MST