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Re: [Qemu-devel] [PATCH v2 1/8] target-arm: A64: add support for ld/st p
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 1/8] target-arm: A64: add support for ld/st pair |
Date: |
Fri, 13 Dec 2013 14:34:46 +0000 |
On 12 December 2013 12:14, C Fontana <address@hidden> wrote:
> I think that there is more than the missing return:
>
> we need to handle the case 0 as well, as it's a perfectly valid form
> of a load/store pair:
> it's the Load/Store no-allocate pair (offset) (LDNP, STNP).
>
> So in my view we need to add a case 0 where we handle the load/store
> no-allocate pair,
> and no default case, or a default case where we assert(0) for unreachable
> code,
> since all possible index values (2 bits) should be handled by the
> switch statement.
Yep. I've added support for the non-temporal versions
(pretty easy since qemu doesn't care about cache allocation
hints) to my patchstack so we'll get this in the next
version of the patchset.
thanks
-- PMM
[Qemu-devel] [PATCH v2 7/8] target-arm: A64: add support for 3 src data proc insns, Peter Maydell, 2013/12/11
[Qemu-devel] [PATCH v2 3/8] target-arm: A64: add support for ld/st with reg offset, Peter Maydell, 2013/12/11
[Qemu-devel] [PATCH v2 6/8] target-arm: A64: add support for move wide instructions, Peter Maydell, 2013/12/11
[Qemu-devel] [PATCH v2 5/8] target-arm: A64: add support for add, addi, sub, subi, Peter Maydell, 2013/12/11