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[Qemu-devel] [PULL 55/62] hw/arm/digic: add NOR ROM support
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 55/62] hw/arm/digic: add NOR ROM support |
Date: |
Tue, 17 Dec 2013 20:29:13 +0000 |
From: Antony Pavlov <address@hidden>
Signed-off-by: Antony Pavlov <address@hidden>
Message-id: address@hidden
[PMM: don't try to load ROM blob if qtest_enabled()]
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/digic_boards.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index 87a9c4b..32fc30a 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -27,6 +27,14 @@
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
#include "hw/arm/digic.h"
+#include "hw/block/flash.h"
+#include "hw/loader.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/qtest.h"
+
+#define DIGIC4_ROM0_BASE 0xf0000000
+#define DIGIC4_ROM1_BASE 0xf8000000
+#define DIGIC4_ROM_MAX_SIZE 0x08000000
typedef struct DigicBoardState {
DigicState *digic;
@@ -35,6 +43,10 @@ typedef struct DigicBoardState {
typedef struct DigicBoard {
hwaddr ram_size;
+ void (*add_rom0)(DigicBoardState *, hwaddr, const char *);
+ const char *rom0_def_filename;
+ void (*add_rom1)(DigicBoardState *, hwaddr, const char *);
+ const char *rom1_def_filename;
} DigicBoard;
static void digic4_board_setup_ram(DigicBoardState *s, hwaddr ram_size)
@@ -59,10 +71,76 @@ static void digic4_board_init(DigicBoard *board)
}
digic4_board_setup_ram(s, board->ram_size);
+
+ if (board->add_rom0) {
+ board->add_rom0(s, DIGIC4_ROM0_BASE, board->rom0_def_filename);
+ }
+
+ if (board->add_rom1) {
+ board->add_rom1(s, DIGIC4_ROM1_BASE, board->rom1_def_filename);
+ }
+}
+
+static void digic_load_rom(DigicBoardState *s, hwaddr addr,
+ hwaddr max_size, const char *def_filename)
+{
+ target_long rom_size;
+ const char *filename;
+
+ if (qtest_enabled()) {
+ /* qtest runs no code so don't attempt a ROM load which
+ * could fail and result in a spurious test failure.
+ */
+ return;
+ }
+
+ if (bios_name) {
+ filename = bios_name;
+ } else {
+ filename = def_filename;
+ }
+
+ if (filename) {
+ char *fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename);
+
+ if (!fn) {
+ error_report("Couldn't find rom image '%s'.\n", filename);
+ exit(1);
+ }
+
+ rom_size = load_image_targphys(fn, addr, max_size);
+ if (rom_size < 0 || rom_size > max_size) {
+ error_report("Couldn't load rom image '%s'.\n", filename);
+ exit(1);
+ }
+ }
+}
+
+/*
+ * Samsung K8P3215UQB
+ * 64M Bit (4Mx16) Page Mode / Multi-Bank NOR Flash Memory
+ */
+static void digic4_add_k8p3215uqb_rom(DigicBoardState *s, hwaddr addr,
+ const char *def_filename)
+{
+#define FLASH_K8P3215UQB_SIZE (4 * 1024 * 1024)
+#define FLASH_K8P3215UQB_SECTOR_SIZE (64 * 1024)
+
+ pflash_cfi02_register(addr, NULL, "pflash", FLASH_K8P3215UQB_SIZE,
+ NULL, FLASH_K8P3215UQB_SECTOR_SIZE,
+ FLASH_K8P3215UQB_SIZE / FLASH_K8P3215UQB_SECTOR_SIZE,
+ DIGIC4_ROM_MAX_SIZE / FLASH_K8P3215UQB_SIZE,
+ 4,
+ 0x00EC, 0x007E, 0x0003, 0x0001,
+ 0x0555, 0x2aa, 0);
+
+ digic_load_rom(s, addr, FLASH_K8P3215UQB_SIZE, def_filename);
}
static DigicBoard digic4_board_canon_a1100 = {
.ram_size = 64 * 1024 * 1024,
+ .add_rom1 = digic4_add_k8p3215uqb_rom,
+ .rom1_def_filename = "canon-a1100-rom1.bin",
};
static void canon_a1100_init(QEMUMachineInitArgs *args)
--
1.8.5
- [Qemu-devel] [PULL 52/62] hw/arm/digic: prepare DIGIC-based boards support, (continued)
- [Qemu-devel] [PULL 52/62] hw/arm/digic: prepare DIGIC-based boards support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 48/62] host-utils: add clrsb32/64 - count leading redundant sign bits, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 47/62] target-arm: A64: add support for bitfield insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 46/62] target-arm: A64: add support for 1-src REV insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 54/62] hw/arm/digic: add UART support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 43/62] target-arm: A64: add support for 2-src shift reg insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 37/62] target-arm: A64: add support for compare and branch imm, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 59/62] hw/intc: add allwinner A10 interrupt controller, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 39/62] target-arm: A64: add support for logical (shifted register), Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 38/62] target-arm: A64: add support for conditional select, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 55/62] hw/arm/digic: add NOR ROM support,
Peter Maydell <=
- [Qemu-devel] [PULL 44/62] target-arm: A64: add support for 1-src data processing and CLZ, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 49/62] target-arm: A64: add support for 1-src CLS insn, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 41/62] target-arm: A64: add support for EXTR, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 22/62] configure: Enable KVM for aarch64 host/target combination, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 26/62] target-arm: Split A64 from A32/T32 gen_intermediate_code_internal(), Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 02/62] rename pflash_t member width to bank_width, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 24/62] hw/arm/boot: Add boot support for AArch64 processor, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 13/62] arm/highbank: Fix CBAR initialisation, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 03/62] Add device-width property to pflash_cfi01, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 23/62] hw/arm/boot: Allow easier swapping in of different loader code, Peter Maydell, 2013/12/17