qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [RFC PATCH 19/21] target-arm: add MVBAR support


From: Peter Crosthwaite
Subject: Re: [Qemu-devel] [RFC PATCH 19/21] target-arm: add MVBAR support
Date: Thu, 19 Dec 2013 14:41:16 +1000

On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov <address@hidden> wrote:
> MVBAR register provides an exception vector base address for exceptions
> taking to CPU monitor mode.
>
> Signed-off-by: Sergey Fedorov <address@hidden>
> ---
>  target-arm/cpu.h    |    1 +
>  target-arm/helper.c |   16 +++++++---------
>  2 files changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index b4500b4..3e5b860 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -210,6 +210,7 @@ typedef struct CPUARMState {
>          uint32_t c9_pmuserenr; /* perf monitor user enable */
>          uint32_t c9_pminten; /* perf monitor interrupt enables */
>          BANKED_CP_REG(uint32_t, c12_vbar); /* vector base address register */
> +        uint32_t c12_mvbar; /* monitor vector base address register */
>          BANKED_CP_REG(uint32_t, c13_fcse); /* FCSE PID.  */
>          BANKED_CP_REG(uint32_t, c13_context); /* Context ID.  */
>          BANKED_CP_REG(uint32_t, c13_tls1); /* User RW Thread register.  */
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 7bfadb0..582de74 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1568,7 +1568,7 @@ static int scr_write(CPUARMState *env, const 
> ARMCPRegInfo *ri, uint64_t value)
>  static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                        uint64_t value)
>  {
> -    env->cp15.c12_vbar = value & ~0x1Ful;
> +    CPREG_FIELD32(env, ri) = value & ~0x1Ful;
>      return 0;
>  }
>
> @@ -1589,6 +1589,9 @@ static const ARMCPRegInfo tz_cp_reginfo[] = {
>        .access = PL1_RW, .type = ARM_CP_BANKED, .writefn = vbar_write,
>        .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
>        .resetvalue = 0 },
> +    { .name = "MVBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1,
> +      .access = PL3_RW, .resetvalue = 0, .writefn = vbar_write,
> +      .fieldoffset = offsetof(CPUARMState, cp15.c12_mvbar) },
>      { .name = "SDER", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 1,
>        .access = PL3_RW, .resetvalue = 0,
>        .fieldoffset = offsetof(CPUARMState, cp15.c1_sder) },
> @@ -2630,17 +2633,12 @@ void arm_cpu_do_interrupt(CPUState *cs)
>          return; /* Never happens.  Keep compiler happy.  */
>      }
>      /* High vectors.  */

Cut this comment ....

> -    if (env->cp15.c1_sys & (1 << 13)) {
> +    if (new_mode == ARM_CPU_MODE_MON) {
> +        addr += env->cp15.c12_mvbar;
> +    } else if (env->cp15.c1_sys & (1 << 13)) {

and paste it back here. Your prepend of the monitor logic makes it
stale in that location.

Regards,
Peter

>          /* when enabled, base address cannot be remapped.  */
>          addr += 0xffff0000;
>      } else {
> -        /* ARM v7 architectures provide a vector base address register to 
> remap
> -         * the interrupt vector table.
> -         * This register is only followed in non-monitor mode, and has a 
> secure
> -         * and un-secure copy. Since the cpu is always in a un-secure 
> operation
> -         * and is never in monitor mode this feature is always active.
> -         * Note: only bits 31:5 are valid.
> -         */
>          addr += env->cp15.c12_vbar;
>      }
>      switch_mode (env, new_mode);
> --
> 1.7.9.5
>
>



reply via email to

[Prev in Thread] Current Thread [Next in Thread]