Re: [Qemu-devel] [RFC PATCH 02/21] target-arm: move SCR & VBAR into TrustZone register list

[Fedorov Sergey]

On 12/19/2013 07:12 AM, Peter Crosthwaite wrote:
> On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov <address@hidden> wrote:
> > Define a new ARM CP register info list for TrustZone Security Extension
> > feature. Register that list only for ARM cores with TrustZone support.
> > SCR and VBAR are security extension registers. So move them into
> > TrustZone feature register list.
> >
> > Signed-off-by: Sergey Fedorov <address@hidden>
> > ---
> >   target-arm/helper.c |   39 +++++++++++++++++++++++++--------------
> >   1 file changed, 25 insertions(+), 14 deletions(-)
> >
> > diff --git a/target-arm/helper.c b/target-arm/helper.c
> > index 3445813..a247ca0 100644
> > --- a/target-arm/helper.c
> > +++ b/target-arm/helper.c
> > @@ -543,13 +543,6 @@ static int pmintenclr_write(CPUARMState *env, const 
> > ARMCPRegInfo *ri,
> >       return 0;
> >   }
> >
> > -static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
> > -                      uint64_t value)
> > -{
> > -    env->cp15.c12_vbar = value & ~0x1Ful;
> > -    return 0;
> > -}
> > -
> >   static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
> >                          uint64_t *value)
> >   {
> > @@ -635,13 +628,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
> >         .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
> >         .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
> >         .resetvalue = 0, .writefn = pmintenclr_write, },
> > -    { .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
> > -      .access = PL1_RW, .writefn = vbar_write,
> > -      .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
> > -      .resetvalue = 0 },
> > -    { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
> > -      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
> > -      .resetvalue = 0, },
> >       { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
> >         .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
> >       { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
> > @@ -1526,6 +1512,28 @@ static int sctlr_write(CPUARMState *env, const 
> > ARMCPRegInfo *ri, uint64_t value)
> >       return 0;
> >   }
> >
> > +#ifndef CONFIG_USER_ONLY
> > +static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
> > +                      uint64_t value)
> > +{
> > +    env->cp15.c12_vbar = value & ~0x1Ful;
> > +    return 0;
> > +}
> > +#endif
> > +
> > +static const ARMCPRegInfo tz_cp_reginfo[] = {
> > +#ifndef CONFIG_USER_ONLY
> > +    { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
> > +      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
> > +      .resetvalue = 0 },
> > +    { .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
> > +      .access = PL1_RW, .writefn = vbar_write,
> > +      .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
> > +      .resetvalue = 0 },
> > +#endif
> > +    REGINFO_SENTINEL
> > +};
> > +
> >   void register_cp_regs_for_features(ARMCPU *cpu)
> >   {
> >       /* Register all the coprocessor registers based on feature bits */
> > @@ -1663,6 +1671,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> >       if (arm_feature(env, ARM_FEATURE_LPAE)) {
> >           define_arm_cp_regs(cpu, lpae_cp_reginfo);
> >       }
> > +    if (arm_feature(env, ARM_FEATURE_TRUSTZONE)) {
> > +        define_arm_cp_regs(cpu, tz_cp_reginfo);
> So ARM docmentation refers to these features as being conditional on
> the "security extensions" option, not "trustzone". To match
> documentation i think it may actually be
> ARM_FEATURE_SECURITY_EXTENSIONS (or some truntaction thereof for
> brevity). On what level of ARM documentation is the "trustzone" term
> defined?
>
> Regards,
> Peter

The "TrustZone" term is not mentioned in ARM architecture manual. That 
is a name for technology of system-wide approach to security. So 
strictly speaking there should be used term "Security Extensions". I 
cannot find any official truncation of this term.

Best regards,
Sergey Fedorov

> > +    }
> >       /* Slightly awkwardly, the OMAP and StrongARM cores need all of
> >        * cp15 crn=0 to be writes-ignored, whereas for other cores they should
> >        * be read-only (ie write causes UNDEF exception).
> > --
> > 1.7.9.5