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[Qemu-devel] [PULL 09/32] Add xxpermdi
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 09/32] Add xxpermdi |
Date: |
Fri, 20 Dec 2013 02:00:31 +0100 |
From: Tom Musta <address@hidden>
This patch adds the xxpermdi instruction. The instruction
uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX
and BX). This results in overloading of the opcode table
with aliases, which can be seen in the GEN_XX3FORM_DM
macro.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Anton Blanchard <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/translate.c | 41 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 30dba74..cf7927b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7035,10 +7035,28 @@ static void gen_stxvd2x(DisasContext *ctx)
tcg_temp_free(EA);
}
+static void gen_xxpermdi(DisasContext *ctx)
+{
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+
+ if ((DM(ctx->opcode) & 2) == 0) {
+ tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
+ } else {
+ tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
+ }
+ if ((DM(ctx->opcode) & 1) == 0) {
+ tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
+ } else {
+ tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
+ }
+}
+
/*** SPE extension ***/
/* Register moves */
-
static inline void gen_evmra(DisasContext *ctx)
{
@@ -9488,6 +9506,27 @@ GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE,
PPC2_VSX),
GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
+#undef GEN_XX3FORM_DM
+#define GEN_XX3FORM_DM(name, opc2, opc3) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE,
PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE,
PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE,
PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE,
PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE,
PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE,
PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE,
PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE,
PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE,
PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE,
PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE,
PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE,
PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE,
PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE,
PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE,
PPC2_VSX),\
+GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
+
+GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
+
#undef GEN_SPE
#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type,
PPC_NONE)
--
1.8.1.4
- [Qemu-devel] [PULL 02/32] powerpc: add PVR mask support, (continued)
- [Qemu-devel] [PULL 02/32] powerpc: add PVR mask support, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 04/32] Add MSR VSX and Associated Exception, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 05/32] Add VSX Instruction Decoders, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 08/32] Add stxvd2x, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 01/32] target-ppc: add stubs for KVM breakpoints, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 03/32] Declare and Enable VSX, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 11/32] Add lxvdsx, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 14/32] Add stxvw4x, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 24/32] Add xxmrgh/xxmrgl, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 10/32] Add lxsdx, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 09/32] Add xxpermdi,
Alexander Graf <=
- [Qemu-devel] [PULL 12/32] Add lxvw4x, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 13/32] Add stxsdx, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 15/32] target-ppc: move POWER7+ to a separate family, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 23/32] Add Power7 VSX Logical Instructions, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 19/32] spapr: tie spapr-nvram to -pflash, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 17/32] spapr-rtas: add ibm, (get|set)-system-parameter, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 18/32] PPC: Use default pci bus name for grackle and heathrow, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 31/32] spapr: make sure RMA is in first mode of first memory node, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 28/32] PPC: Add VSX to hflags, Alexander Graf, 2013/12/19
- [Qemu-devel] [PULL 27/32] Add xxsldwi, Alexander Graf, 2013/12/19