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[Qemu-devel] [PATCH v2 18/25] target-arm: A64: add support for condition
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 18/25] target-arm: A64: add support for conditional compare insns |
Date: |
Sun, 22 Dec 2013 22:50:00 +0000 |
From: Claudio Fontana <address@hidden>
this patch adds support for C3.5.4 - C3.5.5
Conditional compare (both immediate and register)
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate-a64.c | 73 +++++++++++++++++++++++++++++++++++++---------
1 file changed, 60 insertions(+), 13 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 9f508b9..538d69e 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -2483,16 +2483,67 @@ static void disas_adc_sbc(DisasContext *s, uint32_t
insn)
}
}
-/* Conditional compare (immediate) */
-static void disas_cc_imm(DisasContext *s, uint32_t insn)
+/* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
+ * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
+ * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
+ * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
+ * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
+ * [1] y [0] [0]
+ */
+static void disas_cc(DisasContext *s, uint32_t insn)
{
- unsupported_encoding(s, insn);
-}
+ unsigned int sf, op, y, cond, rn, nzcv, is_imm;
+ int label_continue = -1;
+ TCGv_i64 tcg_tmp, tcg_y, tcg_rn;
-/* Conditional compare (register) */
-static void disas_cc_reg(DisasContext *s, uint32_t insn)
-{
- unsupported_encoding(s, insn);
+ if (!extract32(insn, 29, 1)) {
+ unallocated_encoding(s);
+ return;
+ }
+ if (insn & (1 << 10 | 1 << 4)) {
+ unallocated_encoding(s);
+ return;
+ }
+ sf = extract32(insn, 31, 1);
+ op = extract32(insn, 30, 1);
+ is_imm = extract32(insn, 11, 1);
+ y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */
+ cond = extract32(insn, 12, 4);
+ rn = extract32(insn, 5, 5);
+ nzcv = extract32(insn, 0, 4);
+
+ if (cond < 0x0e) { /* not always */
+ int label_match = gen_new_label();
+ label_continue = gen_new_label();
+ arm_gen_test_cc(cond, label_match);
+ /* nomatch: */
+ tcg_tmp = tcg_temp_new_i64();
+ tcg_gen_movi_i64(tcg_tmp, nzcv << 28);
+ gen_set_nzcv(tcg_tmp);
+ tcg_temp_free_i64(tcg_tmp);
+ tcg_gen_br(label_continue);
+ gen_set_label(label_match);
+ }
+ /* match, or condition is always */
+ if (is_imm) {
+ tcg_y = new_tmp_a64(s);
+ tcg_gen_movi_i64(tcg_y, y);
+ } else {
+ tcg_y = cpu_reg(s, y);
+ }
+ tcg_rn = cpu_reg(s, rn);
+
+ tcg_tmp = tcg_temp_new_i64();
+ if (op) {
+ gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y);
+ } else {
+ gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y);
+ }
+ tcg_temp_free_i64(tcg_tmp);
+
+ if (cond < 0x0e) { /* continue */
+ gen_set_label(label_continue);
+ }
}
/* C3.5.6 Conditional select
@@ -2846,11 +2897,7 @@ static void disas_data_proc_reg(DisasContext *s,
uint32_t insn)
disas_adc_sbc(s, insn);
break;
case 0x2: /* Conditional compare */
- if (insn & (1 << 11)) { /* (immediate) */
- disas_cc_imm(s, insn);
- } else { /* (register) */
- disas_cc_reg(s, insn);
- }
+ disas_cc(s, insn); /* both imm and reg forms */
break;
case 0x4: /* Conditional select */
disas_cond_select(s, insn);
--
1.8.5
- [Qemu-devel] [PATCH v2 00/25] target-arm: A64 decoder sets 3 and 4: everything but fp & simd, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 19/25] target-arm: aarch64: add support for ld lit, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 17/25] target-arm: A64: add support for add/sub with carry, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 25/25] default-configs: Add config for aarch64-linux-user, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 23/25] linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 11/25] target-arm: Pull "add one cpreg to hashtable" into its own function, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 10/25] target-arm: A64: implement FMOV, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 04/25] target-arm: A64: add support for ld/st with index, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 18/25] target-arm: A64: add support for conditional compare insns,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 09/25] target-arm: A64: Add decoder skeleton for FP instructions, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 22/25] linux-user: AArch64: define TARGET_CLONE_BACKWARDS, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 08/25] target-arm: A64: implement SVC, BRK, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 12/25] target-arm: Update generic cpreg code for AArch64, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 14/25] target-arm: A64: Implement MRS/MSR/SYS/SYSL, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 05/25] target-arm: A64: add support for add, addi, sub, subi, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 02/25] target-arm: A64: add support for ld/st unsigned imm, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 24/25] .travis.yml: Add aarch64-* targets, Peter Maydell, 2013/12/22