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Re: [Qemu-devel] [PATCH v2 20/25] target-arm: Widen exclusive-access sup
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v2 20/25] target-arm: Widen exclusive-access support struct fields to 64 bits |
Date: |
Mon, 23 Dec 2013 13:27:15 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 |
On 12/22/2013 02:50 PM, Peter Maydell wrote:
> In preparation for adding support for A64 load/store exclusive instructions,
> widen the fields in the CPU state struct that deal with address and data
> values
> for exclusives from 32 to 64 bits. Although in practice AArch64 and AArch32
> exclusive accesses will be generally separate there are some odd theoretical
> corner cases (eg you should be able to do the exclusive load in AArch32, take
> an exception to AArch64 and successfully do the store exclusive there), and
> it's
> also easier to reason about.
>
> The changes in semantics for the variables are:
> exclusive_addr -> extended to 64 bits; -1ULL for "monitor lost",
> otherwise always < 2^32 for AArch32
> exclusive_val -> extended to 64 bits. 64 bit exclusives in AArch32 now
> use the high half of exclusive_val instead of a separate exclusive_high
> exclusive_high -> is no longer used in AArch32; extended to 64 bits as
> it will be needed for AArch64's pair-of-64-bit-values exclusives.
> exclusive_test -> extended to 64 bits, as it is an address. Since this is
> a linux-user-only field, in arm-linux-user it will always have the top
> 32 bits zero.
> exclusive_info -> stays 32 bits, as it is neither data nor address, but
> simply holds register indexes etc. AArch64 will be able to fit all its
> information into 32 bits as well.
>
> Note that the refactoring of gen_store_exclusive() coincidentally fixes
> a minor bug where ldrexd would incorrectly update the first CPU register
> even if the load for the second register faulted.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
Reviewed-by: Richard Henderson <address@hidden>
r~
- [Qemu-devel] [PATCH v2 12/25] target-arm: Update generic cpreg code for AArch64, (continued)
- [Qemu-devel] [PATCH v2 12/25] target-arm: Update generic cpreg code for AArch64, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 14/25] target-arm: A64: Implement MRS/MSR/SYS/SYSL, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 05/25] target-arm: A64: add support for add, addi, sub, subi, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 02/25] target-arm: A64: add support for ld/st unsigned imm, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 24/25] .travis.yml: Add aarch64-* targets, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 15/25] target-arm: A64: Implement minimal set of EL0-visible sysregs, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 01/25] target-arm: A64: add support for ld/st pair, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 06/25] target-arm: A64: add support for move wide instructions, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 20/25] target-arm: Widen exclusive-access support struct fields to 64 bits, Peter Maydell, 2013/12/22
- Re: [Qemu-devel] [PATCH v2 20/25] target-arm: Widen exclusive-access support struct fields to 64 bits,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 16/25] target-arm: Widen thread-local register state fields to 64 bits, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 03/25] target-arm: A64: add support for ld/st with reg offset, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 07/25] target-arm: A64: add support for 3 src data proc insns, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 21/25] target-arm: A64: support for ld/st/cl exclusive, Peter Maydell, 2013/12/22
- [Qemu-devel] [PATCH v2 13/25] target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder, Peter Maydell, 2013/12/22