[Qemu-devel] [PATCH v2 00/10] A64 decoder patchset 5: most floating point

[Peter Maydell]

FP support patchset. Changes v1->v2:
 patch 1: correct format string, argument order issues
 patch 2: simplify do_fp_st by always loading 64 bits from the
   vfp regs entry

patches 3-10 unchanged; all have been reviewed.

This patchset sits on top of the previous one (now almost entirely
codereviewed); you can find a git tree at
 git://git.linaro.org/people/peter.maydell/qemu-arm.git a64-fifth-set
web UI:
 
https://git.linaro.org/people/peter.maydell/qemu-arm.git/shortlog/refs/heads/a64-fifth-set

thanks
-- PMM



*** BLURB HERE ***

Alexander Graf (5):
  target-arm: A64: Add support for dumping AArch64 VFP register state
  target-arm: A64: Add "Floating-point data-processing (2 source)" insns
  target-arm: A64: Add "Floating-point data-processing (3 source)" insns
  target-arm: A64: Add fmov (scalar, immediate) instruction
  target-arm: Give the FPSCR rounding modes names

Claudio Fontana (3):
  target-arm: A64: Add support for floating point compare
  target-arm: A64: Add support for floating point conditional compare
  target-arm: A64: Add support for floating point cond select

Peter Maydell (2):
  target-arm: A64: Fix vector register access on bigendian hosts
  target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum

 target-arm/cpu.h           |   9 +
 target-arm/helper-a64.c    |  45 ++++
 target-arm/helper-a64.h    |   4 +
 target-arm/helper.c        |  37 +---
 target-arm/helper.h        |  15 +-
 target-arm/neon_helper.c   |  12 -
 target-arm/translate-a64.c | 539 +++++++++++++++++++++++++++++++++++++++++----
 target-arm/translate.c     |  16 +-
 8 files changed, 581 insertions(+), 96 deletions(-)

-- 
1.8.5