Re: [Qemu-devel] [PATCH v2 15/25] target-arm: A64: Implement minimal set of EL0-visible sysregs

[Peter Maydell]

On 4 January 2014 13:32, Peter Crosthwaite <address@hidden> wrote:
> On Mon, Dec 23, 2013 at 8:49 AM, Peter Maydell <address@hidden> wrote:
>> +static const ARMCPRegInfo v8_cp_reginfo[] = {
>> +    /* Minimal set of EL0-visible registers. This will need to be expanded
>> +     * significantly for system emulation of AArch64 CPUs.
>> +     */
>> +    { .name = "NZCV", .state = ARM_CP_STATE_AA64,
>> +      .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
>> +      .access = PL0_RW, .type = ARM_CP_NZCV },
>> +    {. name = "FPCR", .state = ARM_CP_STATE_AA64,
>> +     .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
>> +     .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write 
>> },
>> +    {. name = "FPSR", .state = ARM_CP_STATE_AA64,
>> +     .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
>> +     .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write 
>> },
>> +    /* This claims a 32 byte cacheline size for icache and dcache, VIPT 
>> icache.
>> +     * It will eventually need to have a CPU-specified reset value.
>> +     */
>
> Not sure why this can't be solved short term as there is already the
> ctr field in cpu state struct as used by 32.

I hadn't noticed that the register was aliased to the CTR AArch32 register.
NB that we can't just share a single reginfo for AArch64 and AArch32
though -- the permissions are different since in AArch32 this is accessible
only in EL1 and above.

My aim here was mostly to set out a framework for how the system
register integration will work with system emulation, but just to
provide low-effort implementations of the EL0-visible regs for
the initial user-emulation patchset. (In the SuSE patchset these are
actually just all implemented as special cases inline in translate-a64.c,
so to some extent this array is just those special cases converted over
to reginfo.)

thanks
-- PMM