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[Qemu-devel] [PULL 52/52] hw: arm_gic: Introduce gic_set_priority functi
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 52/52] hw: arm_gic: Introduce gic_set_priority function |
Date: |
Mon, 6 Jan 2014 11:30:57 +0000 |
From: Christoffer Dall <address@hidden>
To make the code slightly cleaner to look at and make the save/restore
code easier to understand, introduce this function to set the priority of
interrupts.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Christoffer Dall <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gic.c | 15 ++++++++++-----
hw/intc/gic_internal.h | 1 +
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 27c258a..6c59650 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -168,6 +168,15 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu)
return new_irq;
}
+void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val)
+{
+ if (irq < GIC_INTERNAL) {
+ s->priority1[irq][cpu] = val;
+ } else {
+ s->priority2[(irq) - GIC_INTERNAL] = val;
+ }
+}
+
void gic_complete_irq(GICState *s, int cpu, int irq)
{
int update = 0;
@@ -443,11 +452,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
irq = (offset - 0x400) + GIC_BASE_IRQ;
if (irq >= s->num_irq)
goto bad_reg;
- if (irq < GIC_INTERNAL) {
- s->priority1[irq][cpu] = value;
- } else {
- s->priority2[irq - GIC_INTERNAL] = value;
- }
+ gic_set_priority(s, cpu, irq, value);
} else if (offset < 0xc00) {
/* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
* annoying exception of the 11MPCore's GIC.
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index efac78d..8c02d58 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -61,5 +61,6 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu);
void gic_complete_irq(GICState *s, int cpu, int irq);
void gic_update(GICState *s);
void gic_init_irqs_and_distributor(GICState *s, int num_irq);
+void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val);
#endif /* !QEMU_ARM_GIC_INTERNAL_H */
--
1.8.5
- [Qemu-devel] [PULL 00/52] target-arm queue, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 15/52] target-arm: A64: Implement minimal set of EL0-visible sysregs, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 18/52] target-arm: A64: add support for conditional compare insns, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 17/52] target-arm: A64: add support for add/sub with carry, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 10/52] target-arm: A64: implement FMOV, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 52/52] hw: arm_gic: Introduce gic_set_priority function,
Peter Maydell <=
- [Qemu-devel] [PULL 51/52] arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 16/52] target-arm: Widen thread-local register state fields to 64 bits, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 49/52] arm/xilinx_zynq: Always instantiate the GEMs, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 48/52] target-arm: remove raw_read|write duplication, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 50/52] target-arm: fix build with gcc 4.8.2, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 46/52] char/cadence_uart: Implement Tx flow control, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 43/52] char/cadence_uart: Fix can_receive logic, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 44/52] char/cadence_uart: Use the TX fifo for transmission, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 41/52] char/cadence_uart: Define Missing SR/ISR fields, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 40/52] char/cadence_uart: Simplify status generation, Peter Maydell, 2014/01/06