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[Qemu-devel] [PULL 50/52] target-arm: fix build with gcc 4.8.2
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 50/52] target-arm: fix build with gcc 4.8.2 |
Date: |
Mon, 6 Jan 2014 11:30:55 +0000 |
From: "Michael S. Tsirkin" <address@hidden>
commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
"target-arm: A64: add set_pc cpu method"
introduces an array aarch64_cpus which is zero
size if this code is built without CONFIG_USER_ONLY.
In particular an attempt to iterate over this array produces a warning
under gcc 4.8.2:
CC aarch64-softmmu/target-arm/cpu64.o
/scm/qemu/target-arm/cpu64.c: In function ‘aarch64_cpu_register_types’:
/scm/qemu/target-arm/cpu64.c:124:5: error: comparison of unsigned
expression < 0 is always false [-Werror=type-limits]
for (i = 0; i < ARRAY_SIZE(aarch64_cpus); i++) {
^
cc1: all warnings being treated as errors
This is the result of ARRAY_SIZE being an unsigned type,
causing "i" to be promoted to unsigned int as well.
As zero size arrays are a gcc extension, it seems
cleanest to add a dummy element with NULL name,
and test for it during registration.
We'll be able to drop this when we add more CPUs.
Cc: Alexander Graf <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: Richard Henderson <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Stefan Weil <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu64.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index 04ce879..60acd24 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -58,6 +58,7 @@ static const ARMCPUInfo aarch64_cpus[] = {
#ifdef CONFIG_USER_ONLY
{ .name = "any", .initfn = aarch64_any_initfn },
#endif
+ { .name = NULL } /* TODO: drop when we support more CPUs */
};
static void aarch64_cpu_initfn(Object *obj)
@@ -100,6 +101,11 @@ static void aarch64_cpu_register(const ARMCPUInfo *info)
.class_init = info->class_init,
};
+ /* TODO: drop when we support more CPUs - all entries will have name set */
+ if (!info->name) {
+ return;
+ }
+
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
type_register(&type_info);
g_free((void *)type_info.name);
--
1.8.5
- [Qemu-devel] [PULL 00/52] target-arm queue, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 15/52] target-arm: A64: Implement minimal set of EL0-visible sysregs, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 18/52] target-arm: A64: add support for conditional compare insns, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 17/52] target-arm: A64: add support for add/sub with carry, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 10/52] target-arm: A64: implement FMOV, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 52/52] hw: arm_gic: Introduce gic_set_priority function, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 51/52] arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 16/52] target-arm: Widen thread-local register state fields to 64 bits, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 49/52] arm/xilinx_zynq: Always instantiate the GEMs, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 48/52] target-arm: remove raw_read|write duplication, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 50/52] target-arm: fix build with gcc 4.8.2,
Peter Maydell <=
- [Qemu-devel] [PULL 46/52] char/cadence_uart: Implement Tx flow control, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 43/52] char/cadence_uart: Fix can_receive logic, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 44/52] char/cadence_uart: Use the TX fifo for transmission, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 41/52] char/cadence_uart: Define Missing SR/ISR fields, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 40/52] char/cadence_uart: Simplify status generation, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 39/52] char/cadence_uart: s/r_fifo/rx_fifo, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 38/52] char/cadence_uart: Fix reset., Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 37/52] char/cadence_uart: Add missing uart_update_state, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 47/52] target-arm: use c13_context field for CONTEXTIDR, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 36/52] char/cadence_uart: Mark struct fields as public/private, Peter Maydell, 2014/01/06