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[Qemu-devel] [PULL 40/52] char/cadence_uart: Simplify status generation
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 40/52] char/cadence_uart: Simplify status generation |
Date: |
Mon, 6 Jan 2014 11:30:45 +0000 |
From: Peter Crosthwaite <address@hidden>
The status register bits are always pure functions of other device
state. Move the generation of these bits to the update_status()
function to simplify. Makes developing much easier as theres now no need
to recheck status bits on all the changes to rx/tx fifo state.
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/char/cadence_uart.c | 33 ++++++++-------------------------
1 file changed, 8 insertions(+), 25 deletions(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index d6abc5b..ddd7267 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -128,6 +128,13 @@ typedef struct {
static void uart_update_status(UartState *s)
{
+ s->r[R_SR] = 0;
+
+ s->r[R_SR] |= s->rx_count == RX_FIFO_SIZE ? UART_SR_INTR_RFUL : 0;
+ s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
+ s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
+
+ s->r[R_SR] |= UART_SR_INTR_TEMPTY;
s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
}
@@ -166,15 +173,10 @@ static void uart_rx_reset(UartState *s)
if (s->chr) {
qemu_chr_accept_input(s->chr);
}
-
- s->r[R_SR] |= UART_SR_INTR_REMPTY;
- s->r[R_SR] &= ~UART_SR_INTR_RFUL;
}
static void uart_tx_reset(UartState *s)
{
- s->r[R_SR] |= UART_SR_INTR_TEMPTY;
- s->r[R_SR] &= ~UART_SR_INTR_TFUL;
}
static void uart_send_breaks(UartState *s)
@@ -274,8 +276,6 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t
*buf, int size)
return;
}
- s->r[R_SR] &= ~UART_SR_INTR_REMPTY;
-
if (s->rx_count == RX_FIFO_SIZE) {
s->r[R_CISR] |= UART_INTR_ROVR;
} else {
@@ -283,15 +283,6 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t
*buf, int size)
s->rx_fifo[s->rx_wpos] = buf[i];
s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE;
s->rx_count++;
-
- if (s->rx_count == RX_FIFO_SIZE) {
- s->r[R_SR] |= UART_SR_INTR_RFUL;
- break;
- }
-
- if (s->rx_count >= s->r[R_RTRIG]) {
- s->r[R_SR] |= UART_SR_INTR_RTRIG;
- }
}
timer_mod(s->fifo_trigger_handle, new_rx_time +
(s->char_tx_time * 4));
@@ -339,26 +330,17 @@ static void uart_read_rx_fifo(UartState *s, uint32_t *c)
return;
}
- s->r[R_SR] &= ~UART_SR_INTR_RFUL;
-
if (s->rx_count) {
uint32_t rx_rpos =
(RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE;
*c = s->rx_fifo[rx_rpos];
s->rx_count--;
- if (!s->rx_count) {
- s->r[R_SR] |= UART_SR_INTR_REMPTY;
- }
qemu_chr_accept_input(s->chr);
} else {
*c = 0;
- s->r[R_SR] |= UART_SR_INTR_REMPTY;
}
- if (s->rx_count < s->r[R_RTRIG]) {
- s->r[R_SR] &= ~UART_SR_INTR_RTRIG;
- }
uart_update_status(s);
}
@@ -447,6 +429,7 @@ static void cadence_uart_reset(DeviceState *dev)
s->rx_count = 0;
s->rx_wpos = 0;
+ uart_update_status(s);
}
static int cadence_uart_init(SysBusDevice *dev)
--
1.8.5
- [Qemu-devel] [PULL 52/52] hw: arm_gic: Introduce gic_set_priority function, (continued)
- [Qemu-devel] [PULL 52/52] hw: arm_gic: Introduce gic_set_priority function, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 51/52] arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 16/52] target-arm: Widen thread-local register state fields to 64 bits, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 49/52] arm/xilinx_zynq: Always instantiate the GEMs, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 48/52] target-arm: remove raw_read|write duplication, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 50/52] target-arm: fix build with gcc 4.8.2, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 46/52] char/cadence_uart: Implement Tx flow control, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 43/52] char/cadence_uart: Fix can_receive logic, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 44/52] char/cadence_uart: Use the TX fifo for transmission, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 41/52] char/cadence_uart: Define Missing SR/ISR fields, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 40/52] char/cadence_uart: Simplify status generation,
Peter Maydell <=
- [Qemu-devel] [PULL 39/52] char/cadence_uart: s/r_fifo/rx_fifo, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 38/52] char/cadence_uart: Fix reset., Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 37/52] char/cadence_uart: Add missing uart_update_state, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 47/52] target-arm: use c13_context field for CONTEXTIDR, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 36/52] char/cadence_uart: Mark struct fields as public/private, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 35/52] target-arm: Give the FPSCR rounding modes names, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 34/52] target-arm: A64: Add support for floating point cond select, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 33/52] target-arm: A64: Add support for floating point conditional compare, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 45/52] char/cadence_uart: Delete redundant rx rst logic, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 31/52] target-arm: A64: Add fmov (scalar, immediate) instruction, Peter Maydell, 2014/01/06