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[Qemu-devel] [PULL 31/52] target-arm: A64: Add fmov (scalar, immediate)
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 31/52] target-arm: A64: Add fmov (scalar, immediate) instruction |
Date: |
Mon, 6 Jan 2014 11:30:36 +0000 |
From: Alexander Graf <address@hidden>
This patch adds emulation for the fmov instruction working on scalars
with an immediate payload.
Signed-off-by: Alexander Graf <address@hidden>
[WN: Commit message tweak, rebase and use new infrastructure.]
Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 32 +++++++++++++++++++++++++++++++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 84497dc..bb36a66 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3479,7 +3479,37 @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
*/
static void disas_fp_imm(DisasContext *s, uint32_t insn)
{
- unsupported_encoding(s, insn);
+ int rd = extract32(insn, 0, 5);
+ int imm8 = extract32(insn, 13, 8);
+ int is_double = extract32(insn, 22, 2);
+ uint64_t imm;
+ TCGv_i64 tcg_res;
+
+ if (is_double > 1) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ /* The imm8 encodes the sign bit, enough bits to represent
+ * an exponent in the range 01....1xx to 10....0xx,
+ * and the most significant 4 bits of the mantissa; see
+ * VFPExpandImm() in the v8 ARM ARM.
+ */
+ if (is_double) {
+ imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
+ (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
+ extract32(imm8, 0, 6);
+ imm <<= 48;
+ } else {
+ imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
+ (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
+ (extract32(imm8, 0, 6) << 3);
+ imm <<= 16;
+ }
+
+ tcg_res = tcg_const_i64(imm);
+ write_fp_dreg(s, rd, tcg_res);
+ tcg_temp_free_i64(tcg_res);
}
/* C3.6.29 Floating point <-> fixed point conversions
--
1.8.5
- [Qemu-devel] [PULL 40/52] char/cadence_uart: Simplify status generation, (continued)
- [Qemu-devel] [PULL 40/52] char/cadence_uart: Simplify status generation, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 39/52] char/cadence_uart: s/r_fifo/rx_fifo, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 38/52] char/cadence_uart: Fix reset., Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 37/52] char/cadence_uart: Add missing uart_update_state, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 47/52] target-arm: use c13_context field for CONTEXTIDR, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 36/52] char/cadence_uart: Mark struct fields as public/private, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 35/52] target-arm: Give the FPSCR rounding modes names, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 34/52] target-arm: A64: Add support for floating point cond select, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 33/52] target-arm: A64: Add support for floating point conditional compare, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 45/52] char/cadence_uart: Delete redundant rx rst logic, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 31/52] target-arm: A64: Add fmov (scalar, immediate) instruction,
Peter Maydell <=
- [Qemu-devel] [PULL 42/52] char/cadence_uart: Remove TX timer & add TX FIFO state, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 30/52] target-arm: A64: Add "Floating-point data-processing (3 source)" insns, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 26/52] target-arm: A64: Add support for dumping AArch64 VFP register state, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 28/52] target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 27/52] target-arm: A64: Fix vector register access on bigendian hosts, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 32/52] target-arm: A64: Add support for floating point compare, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 24/52] .travis.yml: Add aarch64-* targets, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 25/52] default-configs: Add config for aarch64-linux-user, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 21/52] target-arm: A64: support for ld/st/cl exclusive, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 08/52] target-arm: A64: implement SVC, BRK, Peter Maydell, 2014/01/06