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[Qemu-devel] [PATCH v2 08/24] softfloat: Add float32_to_uint64()
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 08/24] softfloat: Add float32_to_uint64() |
Date: |
Mon, 6 Jan 2014 13:11:05 +0000 |
From: Tom Musta <address@hidden>
This patch adds the float32_to_uint64() routine, which converts a
32-bit floating point number to an unsigned 64 bit number.
This contribution can be licensed under either the softfloat-2a or -2b
license.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
fpu/softfloat.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 1 +
2 files changed, 47 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index d2e9095..55c3ce1 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -1559,6 +1559,52 @@ int64 float32_to_int64( float32 a STATUS_PARAM )
/*----------------------------------------------------------------------------
| Returns the result of converting the single-precision floating-point value
+| `a' to the 64-bit unsigned integer format. The conversion is
+| performed according to the IEC/IEEE Standard for Binary Floating-Point
+| Arithmetic---which means in particular that the conversion is rounded
+| according to the current rounding mode. If `a' is a NaN, the largest
+| unsigned integer is returned. Otherwise, if the conversion overflows, the
+| largest unsigned integer is returned. If the 'a' is negative, the result
+| is rounded and zero is returned; values that do not round to zero will
+| raise the inexact exception flag.
+*----------------------------------------------------------------------------*/
+
+uint64 float32_to_uint64(float32 a STATUS_PARAM)
+{
+ flag aSign;
+ int_fast16_t aExp, shiftCount;
+ uint32_t aSig;
+ uint64_t aSig64, aSigExtra;
+ a = float32_squash_input_denormal(a STATUS_VAR);
+
+ aSig = extractFloat32Frac(a);
+ aExp = extractFloat32Exp(a);
+ aSign = extractFloat32Sign(a);
+ if ((aSign) && (aExp > 126)) {
+ float_raise(float_flag_invalid STATUS_VAR);
+ if (float32_is_any_nan(a)) {
+ return (int64_t)LIT64(0xFFFFFFFFFFFFFFFF);
+ } else {
+ return 0;
+ }
+ }
+ shiftCount = 0xBE - aExp;
+ if (aExp) {
+ aSig |= 0x00800000;
+ }
+ if (shiftCount < 0) {
+ float_raise(float_flag_invalid STATUS_VAR);
+ return (int64_t)LIT64(0xFFFFFFFFFFFFFFFF);
+ }
+
+ aSig64 = aSig;
+ aSig64 <<= 40;
+ shift64ExtraRightJamming(aSig64, 0, shiftCount, &aSig64, &aSigExtra);
+ return roundAndPackUint64(aSign, aSig64, aSigExtra STATUS_VAR);
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the single-precision floating-point value
| `a' to the 64-bit two's complement integer format. The conversion is
| performed according to the IEC/IEEE Standard for Binary Floating-Point
| Arithmetic, except that the conversion is always rounded toward zero. If
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 78b1656..eb81c3b 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -295,6 +295,7 @@ int32 float32_to_int32_round_to_zero( float32 STATUS_PARAM
);
uint32 float32_to_uint32( float32 STATUS_PARAM );
uint32 float32_to_uint32_round_to_zero( float32 STATUS_PARAM );
int64 float32_to_int64( float32 STATUS_PARAM );
+uint64 float32_to_uint64(float32 STATUS_PARAM);
int64 float32_to_int64_round_to_zero( float32 STATUS_PARAM );
float64 float32_to_float64( float32 STATUS_PARAM );
floatx80 float32_to_floatx80( float32 STATUS_PARAM );
--
1.8.5
- Re: [Qemu-devel] [PATCH v2 16/24] softfloat: Add support for ties-away rounding, (continued)
- [Qemu-devel] [PATCH v2 10/24] softfloat: Fix float64_to_uint32, Peter Maydell, 2014/01/06
- [Qemu-devel] [PATCH v2 12/24] softfloat: Provide complete set of accessors for fp state, Peter Maydell, 2014/01/06
- [Qemu-devel] [PATCH v2 03/24] softfloat: Add 16 bit integer to float conversions, Peter Maydell, 2014/01/06
- [Qemu-devel] [PATCH v2 09/24] softfloat: Fix float64_to_uint64_round_to_zero, Peter Maydell, 2014/01/06
- [Qemu-devel] [PATCH v2 11/24] softfloat: Fix float64_to_uint32_round_to_zero, Peter Maydell, 2014/01/06
- [Qemu-devel] [PATCH v2 18/24] target-arm: Rename A32 VFP conversion helpers, Peter Maydell, 2014/01/06
- [Qemu-devel] [PATCH v2 05/24] softfloat: Fix float64_to_uint64, Peter Maydell, 2014/01/06
- [Qemu-devel] [PATCH v2 08/24] softfloat: Add float32_to_uint64(),
Peter Maydell <=
- [Qemu-devel] [PATCH v2 13/24] softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal, Peter Maydell, 2014/01/06
- [Qemu-devel] [PATCH v2 21/24] target-arm: A64: Add "Floating-point<->fixed-point" instructions, Peter Maydell, 2014/01/06
- [Qemu-devel] [PATCH v2 19/24] target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion, Peter Maydell, 2014/01/06
- [Qemu-devel] [PATCH v2 24/24] target-arm: A64: Add support for FCVT between half, single and double, Peter Maydell, 2014/01/06
- [Qemu-devel] [PATCH v2 14/24] softfloat: Add float16 <=> float64 conversion functions, Peter Maydell, 2014/01/06