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[Qemu-devel] [V4 PATCH 16/22] softfloat: Add support for ties-away round
From: |
Tom Musta |
Subject: |
[Qemu-devel] [V4 PATCH 16/22] softfloat: Add support for ties-away rounding |
Date: |
Tue, 7 Jan 2014 10:06:04 -0600 |
From: Peter Maydell <address@hidden>
IEEE754-2008 specifies a new rounding mode:
"roundTiesToAway: the floating-point number nearest to the infinitely
precise result shall be delivered; if the two nearest floating-point
numbers bracketing an unrepresentable infinitely precise result are
equally near, the one with larger magnitude shall be delivered."
Implement this new mode (it is needed for ARM). The general principle
is that the required code is exactly like the ties-to-even code,
except that we do not need to do the "in case of exact tie clear LSB
to round-to-even", because the rounding operation naturally causes
the exact tie to round up in magnitude.
Signed-off-by: Peter Maydell <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
fpu/softfloat.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 3 +-
2 files changed, 56 insertions(+), 1 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 4390e1d..cbad9a7 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -126,6 +126,7 @@ static int32 roundAndPackInt32( flag zSign, uint64_t absZ
STATUS_PARAM)
roundNearestEven = ( roundingMode == float_round_nearest_even );
switch (roundingMode) {
case float_round_nearest_even:
+ case float_round_ties_away:
roundIncrement = 0x40;
break;
case float_round_to_zero:
@@ -175,6 +176,7 @@ static int64 roundAndPackInt64( flag zSign, uint64_t absZ0,
uint64_t absZ1 STATU
roundNearestEven = ( roundingMode == float_round_nearest_even );
switch (roundingMode) {
case float_round_nearest_even:
+ case float_round_ties_away:
increment = ((int64_t) absZ1 < 0);
break;
case float_round_to_zero:
@@ -228,6 +230,7 @@ static int64 roundAndPackUint64(flag zSign, uint64_t absZ0,
roundNearestEven = (roundingMode == float_round_nearest_even);
switch (roundingMode) {
case float_round_nearest_even:
+ case float_round_ties_away:
increment = ((int64_t)absZ1 < 0);
break;
case float_round_to_zero:
@@ -380,6 +383,7 @@ static float32 roundAndPackFloat32(flag zSign, int_fast16_t
zExp, uint32_t zSig
roundNearestEven = ( roundingMode == float_round_nearest_even );
switch (roundingMode) {
case float_round_nearest_even:
+ case float_round_ties_away:
roundIncrement = 0x40;
break;
case float_round_to_zero:
@@ -564,6 +568,7 @@ static float64 roundAndPackFloat64(flag zSign, int_fast16_t
zExp, uint64_t zSig
roundNearestEven = ( roundingMode == float_round_nearest_even );
switch (roundingMode) {
case float_round_nearest_even:
+ case float_round_ties_away:
roundIncrement = 0x200;
break;
case float_round_to_zero:
@@ -748,6 +753,7 @@ static floatx80
zSig0 |= ( zSig1 != 0 );
switch (roundingMode) {
case float_round_nearest_even:
+ case float_round_ties_away:
break;
case float_round_to_zero:
roundIncrement = 0;
@@ -808,6 +814,7 @@ static floatx80
precision80:
switch (roundingMode) {
case float_round_nearest_even:
+ case float_round_ties_away:
increment = ((int64_t)zSig1 < 0);
break;
case float_round_to_zero:
@@ -852,6 +859,7 @@ static floatx80
if ( zSig1 ) STATUS(float_exception_flags) |= float_flag_inexact;
switch (roundingMode) {
case float_round_nearest_even:
+ case float_round_ties_away:
increment = ((int64_t)zSig1 < 0);
break;
case float_round_to_zero:
@@ -1066,6 +1074,7 @@ static float128
roundNearestEven = ( roundingMode == float_round_nearest_even );
switch (roundingMode) {
case float_round_nearest_even:
+ case float_round_ties_away:
increment = ((int64_t)zSig2 < 0);
break;
case float_round_to_zero:
@@ -1128,6 +1137,7 @@ static float128
if ( isTiny && zSig2 ) float_raise( float_flag_underflow
STATUS_VAR);
switch (roundingMode) {
case float_round_nearest_even:
+ case float_round_ties_away:
increment = ((int64_t)zSig2 < 0);
break;
case float_round_to_zero:
@@ -1799,6 +1809,11 @@ float32 float32_round_to_int( float32 a STATUS_PARAM)
return packFloat32( aSign, 0x7F, 0 );
}
break;
+ case float_round_ties_away:
+ if (aExp == 0x7E) {
+ return packFloat32(aSign, 0x7F, 0);
+ }
+ break;
case float_round_down:
return make_float32(aSign ? 0xBF800000 : 0);
case float_round_up:
@@ -1817,6 +1832,9 @@ float32 float32_round_to_int( float32 a STATUS_PARAM)
z &= ~lastBitMask;
}
break;
+ case float_round_ties_away:
+ z += lastBitMask >> 1;
+ break;
case float_round_to_zero:
break;
case float_round_up:
@@ -3197,6 +3215,9 @@ static float32 roundAndPackFloat16(flag zSign,
int_fast16_t zExp,
increment = zSig & (increment << 1);
}
break;
+ case float_round_ties_away:
+ increment = (mask + 1) >> 1;
+ break;
case float_round_up:
increment = zSign ? 0 : mask;
break;
@@ -3426,6 +3447,11 @@ float64 float64_round_to_int( float64 a STATUS_PARAM )
return packFloat64( aSign, 0x3FF, 0 );
}
break;
+ case float_round_ties_away:
+ if (aExp == 0x3FE) {
+ return packFloat64(aSign, 0x3ff, 0);
+ }
+ break;
case float_round_down:
return make_float64(aSign ? LIT64( 0xBFF0000000000000 ) : 0);
case float_round_up:
@@ -3445,6 +3471,9 @@ float64 float64_round_to_int( float64 a STATUS_PARAM )
z &= ~lastBitMask;
}
break;
+ case float_round_ties_away:
+ z += lastBitMask >> 1;
+ break;
case float_round_to_zero:
break;
case float_round_up:
@@ -4710,6 +4739,11 @@ floatx80 floatx80_round_to_int( floatx80 a STATUS_PARAM )
packFloatx80( aSign, 0x3FFF, LIT64( 0x8000000000000000 ) );
}
break;
+ case float_round_ties_away:
+ if (aExp == 0x3FFE) {
+ return packFloatx80(aSign, 0x3FFF, LIT64(0x8000000000000000));
+ }
+ break;
case float_round_down:
return
aSign ?
@@ -4733,6 +4767,9 @@ floatx80 floatx80_round_to_int( floatx80 a STATUS_PARAM )
z.low &= ~lastBitMask;
}
break;
+ case float_round_ties_away:
+ z.low += lastBitMask >> 1;
+ break;
case float_round_to_zero:
break;
case float_round_up:
@@ -5801,6 +5838,15 @@ float128 float128_round_to_int( float128 a STATUS_PARAM )
}
}
break;
+ case float_round_ties_away:
+ if (lastBitMask) {
+ add128(z.high, z.low, 0, lastBitMask >> 1, &z.high, &z.low);
+ } else {
+ if ((int64_t) z.low < 0) {
+ ++z.high;
+ }
+ }
+ break;
case float_round_to_zero:
break;
case float_round_up:
@@ -5832,6 +5878,11 @@ float128 float128_round_to_int( float128 a STATUS_PARAM )
return packFloat128( aSign, 0x3FFF, 0, 0 );
}
break;
+ case float_round_ties_away:
+ if (aExp == 0x3FFE) {
+ return packFloat128(aSign, 0x3FFF, 0, 0);
+ }
+ break;
case float_round_down:
return
aSign ? packFloat128( 1, 0x3FFF, 0, 0 )
@@ -5855,6 +5906,9 @@ float128 float128_round_to_int( float128 a STATUS_PARAM )
z.high &= ~ lastBitMask;
}
break;
+ case float_round_ties_away:
+ z.high += lastBitMask>>1;
+ break;
case float_round_to_zero:
break;
case float_round_up:
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 080b36d..18ef187 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -152,7 +152,8 @@ enum {
float_round_nearest_even = 0,
float_round_down = 1,
float_round_up = 2,
- float_round_to_zero = 3
+ float_round_to_zero = 3,
+ float_round_ties_away = 4,
};
/*----------------------------------------------------------------------------
--
1.7.1
- [Qemu-devel] [V4 PATCH 08/22] target-ppc: Add ISA2.06 lbarx, lharx Instructions, (continued)
- [Qemu-devel] [V4 PATCH 08/22] target-ppc: Add ISA2.06 lbarx, lharx Instructions, Tom Musta, 2014/01/07
- [Qemu-devel] [V4 PATCH 09/22] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions, Tom Musta, 2014/01/07
- [Qemu-devel] [V4 PATCH 13/22] softfloat: Fix exception flag handling for float32_to_float16(), Tom Musta, 2014/01/07
- [Qemu-devel] [V4 PATCH 10/22] target-ppc: Add Flag for ISA V2.06 Floating Point Conversion, Tom Musta, 2014/01/07
- [Qemu-devel] [V4 PATCH 11/22] target-ppc: Add ISA2.06 Float to Integer Instructions, Tom Musta, 2014/01/07
- [Qemu-devel] [V4 PATCH 12/22] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions, Tom Musta, 2014/01/07
- [Qemu-devel] [V4 PATCH 14/22] softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal, Tom Musta, 2014/01/07
- [Qemu-devel] [V4 PATCH 15/22] softfloat: Refactor code handling various rounding modes, Tom Musta, 2014/01/07
- [Qemu-devel] [V4 PATCH 16/22] softfloat: Add support for ties-away rounding,
Tom Musta <=
- [Qemu-devel] [V4 PATCH 17/22] target-ppc: Fix and enable fri[mnpz], Tom Musta, 2014/01/07
- [Qemu-devel] [V4 PATCH 18/22] target-ppc: Add Flag for Power ISA V2.06 Floating Point Test Instructions, Tom Musta, 2014/01/07
- [Qemu-devel] [V4 PATCH 19/22] target-ppc: Add ISA 2.06 ftdiv Instruction, Tom Musta, 2014/01/07
- [Qemu-devel] [V4 PATCH 20/22] target-ppc: Add ISA 2.06 ftsqrt, Tom Musta, 2014/01/07
- [Qemu-devel] [V4 PATCH 21/22] target-ppc: Enable frsqrtes on Power7 and Power8, Tom Musta, 2014/01/07
- [Qemu-devel] [V4 PATCH 22/22] target-ppc: Add ISA2.06 lfiwzx Instruction, Tom Musta, 2014/01/07