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[Qemu-devel] [PULL 34/76] target-arm: A64: Add support for floating poin
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 34/76] target-arm: A64: Add support for floating point cond select |
Date: |
Tue, 7 Jan 2014 20:03:30 +0000 |
From: Claudio Fontana <address@hidden>
This adds decoding support for C3.6.24 FP conditional select.
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 45 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 44d8a09..c9fbf0f 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3304,6 +3304,20 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t
insn)
}
}
+/* copy src FP register to dst FP register; type specifies single or double */
+static void gen_mov_fp2fp(DisasContext *s, int type, int dst, int src)
+{
+ if (type) {
+ TCGv_i64 v = read_fp_dreg(s, src);
+ write_fp_dreg(s, dst, v);
+ tcg_temp_free_i64(v);
+ } else {
+ TCGv_i32 v = read_fp_sreg(s, src);
+ write_fp_sreg(s, dst, v);
+ tcg_temp_free_i32(v);
+ }
+}
+
/* C3.6.24 Floating point conditional select
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
* +---+---+---+-----------+------+---+------+------+-----+------+------+
@@ -3312,7 +3326,36 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t
insn)
*/
static void disas_fp_csel(DisasContext *s, uint32_t insn)
{
- unsupported_encoding(s, insn);
+ unsigned int mos, type, rm, cond, rn, rd;
+ int label_continue = -1;
+
+ mos = extract32(insn, 29, 3);
+ type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
+ rm = extract32(insn, 16, 5);
+ cond = extract32(insn, 12, 4);
+ rn = extract32(insn, 5, 5);
+ rd = extract32(insn, 0, 5);
+
+ if (mos || type > 1) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ if (cond < 0x0e) { /* not always */
+ int label_match = gen_new_label();
+ label_continue = gen_new_label();
+ arm_gen_test_cc(cond, label_match);
+ /* nomatch: */
+ gen_mov_fp2fp(s, type, rd, rm);
+ tcg_gen_br(label_continue);
+ gen_set_label(label_match);
+ }
+
+ gen_mov_fp2fp(s, type, rd, rn);
+
+ if (cond < 0x0e) { /* continue */
+ gen_set_label(label_continue);
+ }
}
/* C3.6.25 Floating point data-processing (1 source)
--
1.8.5
- [Qemu-devel] [PULL 49/76] arm/xilinx_zynq: Always instantiate the GEMs, (continued)
- [Qemu-devel] [PULL 49/76] arm/xilinx_zynq: Always instantiate the GEMs, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 62/76] softfloat: Fix float64_to_uint32, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 63/76] softfloat: Fix float64_to_uint32_round_to_zero, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 47/76] target-arm: use c13_context field for CONTEXTIDR, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 64/76] softfloat: Provide complete set of accessors for fp state, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 20/76] target-arm: Widen exclusive-access support struct fields to 64 bits, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 48/76] target-arm: remove raw_read|write duplication, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 19/76] target-arm: aarch64: add support for ld lit, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 23/76] linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 35/76] target-arm: Give the FPSCR rounding modes names, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 34/76] target-arm: A64: Add support for floating point cond select,
Peter Maydell <=
- [Qemu-devel] [PULL 36/76] char/cadence_uart: Mark struct fields as public/private, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 56/76] softfloat: Make the int-to-float functions take exact-width types, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 13/76] target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 01/76] target-arm: A64: add support for ld/st pair, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 07/76] target-arm: A64: add support for 3 src data proc insns, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 06/76] target-arm: A64: add support for move wide instructions, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 05/76] target-arm: A64: add support for add, addi, sub, subi, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 25/76] default-configs: Add config for aarch64-linux-user, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 26/76] target-arm: A64: Add support for dumping AArch64 VFP register state, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 17/76] target-arm: A64: add support for add/sub with carry, Peter Maydell, 2014/01/07