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[Qemu-devel] [PULL 22/76] linux-user: AArch64: define TARGET_CLONE_BACKW
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 22/76] linux-user: AArch64: define TARGET_CLONE_BACKWARDS |
Date: |
Tue, 7 Jan 2014 20:03:18 +0000 |
From: Claudio Fontana <address@hidden>
The AArch64 linux-user support was written before but merged after
commit 4ce6243dc621 which cleaned up the handling of the clone()
syscall argument order, so we failed to notice that AArch64 also needs
TARGET_CLONE_BACKWARDS to be defined. Add this define so that clone
and fork syscalls work correctly.
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
linux-user/aarch64/syscall.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-user/aarch64/syscall.h b/linux-user/aarch64/syscall.h
index aef419e..18f44a8 100644
--- a/linux-user/aarch64/syscall.h
+++ b/linux-user/aarch64/syscall.h
@@ -7,3 +7,4 @@ struct target_pt_regs {
#define UNAME_MACHINE "aarch64"
#define UNAME_MINIMUM_RELEASE "3.8.0"
+#define TARGET_CLONE_BACKWARDS
--
1.8.5
- Re: [Qemu-devel] [PULL 16/76] target-arm: Widen thread-local register state fields to 64 bits, (continued)
- [Qemu-devel] [PULL 21/76] target-arm: A64: support for ld/st/cl exclusive, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 02/76] target-arm: A64: add support for ld/st unsigned imm, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 15/76] target-arm: A64: Implement minimal set of EL0-visible sysregs, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 04/76] target-arm: A64: add support for ld/st with index, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 08/76] target-arm: A64: implement SVC, BRK, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 74/76] target-arm: A64: Add floating-point<->integer conversion instructions, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 32/76] target-arm: A64: Add support for floating point compare, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 37/76] char/cadence_uart: Add missing uart_update_state, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 14/76] target-arm: A64: Implement MRS/MSR/SYS/SYSL, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 22/76] linux-user: AArch64: define TARGET_CLONE_BACKWARDS,
Peter Maydell <=
- [Qemu-devel] [PULL 57/76] softfloat: Fix float64_to_uint64, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 30/76] target-arm: A64: Add "Floating-point data-processing (3 source)" insns, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 33/76] target-arm: A64: Add support for floating point conditional compare, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 38/76] char/cadence_uart: Fix reset., Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 24/76] .travis.yml: Add aarch64-* targets, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 27/76] target-arm: A64: Fix vector register access on bigendian hosts, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 50/76] target-arm: fix build with gcc 4.8.2, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 39/76] char/cadence_uart: s/r_fifo/rx_fifo, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 31/76] target-arm: A64: Add fmov (scalar, immediate) instruction, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 58/76] softfloat: Only raise Invalid when conversions to int are out of range, Peter Maydell, 2014/01/07