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[Qemu-devel] [PULL 69/76] target-arm: Prepare VFP_CONV_FIX helpers for A
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 69/76] target-arm: Prepare VFP_CONV_FIX helpers for A64 uses |
Date: |
Tue, 7 Jan 2014 20:04:05 +0000 |
From: Will Newton <address@hidden>
Make the VFP_CONV_FIX helpers a little more flexible in
preparation for the A64 uses. This requires two changes:
* use the correct softfloat conversion function based on itype
rather than always the int32 one; this is possible now that
softfloat provides int16 versions and necessary for the
future conversion-to-int64 A64 variants. This also allows
us to drop the awkward 'sign' macro argument.
* split the 'fsz' argument which currently controls both
width of the input float type and width of the output
integer type into two; this will allow us to specify the
A64 64-bit-int-to-single conversion function, where the
two widths are different.
We can also drop the (itype##_t) cast now that softfloat
guarantees that all the itype##_to_float* functions take
an integer argument of exactly the correct type.
Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/helper.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6f629f3..5579565 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3976,17 +3976,17 @@ float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState
*env)
}
/* VFP3 fixed point conversion. */
-#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
-float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
- void *fpstp) \
+#define VFP_CONV_FIX(name, p, fsz, isz, itype) \
+float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
+ void *fpstp) \
{ \
float_status *fpst = fpstp; \
float##fsz tmp; \
- tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
+ tmp = itype##_to_##float##fsz(x, fpst); \
return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
} \
-uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
- void *fpstp) \
+uint##isz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
+ void *fpstp) \
{ \
float_status *fpst = fpstp; \
float##fsz tmp; \
@@ -3998,14 +3998,14 @@ uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x,
uint32_t shift, \
return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
}
-VFP_CONV_FIX(sh, d, 64, int16, )
-VFP_CONV_FIX(sl, d, 64, int32, )
-VFP_CONV_FIX(uh, d, 64, uint16, u)
-VFP_CONV_FIX(ul, d, 64, uint32, u)
-VFP_CONV_FIX(sh, s, 32, int16, )
-VFP_CONV_FIX(sl, s, 32, int32, )
-VFP_CONV_FIX(uh, s, 32, uint16, u)
-VFP_CONV_FIX(ul, s, 32, uint32, u)
+VFP_CONV_FIX(sh, d, 64, 64, int16)
+VFP_CONV_FIX(sl, d, 64, 64, int32)
+VFP_CONV_FIX(uh, d, 64, 64, uint16)
+VFP_CONV_FIX(ul, d, 64, 64, uint32)
+VFP_CONV_FIX(sh, s, 32, 32, int16)
+VFP_CONV_FIX(sl, s, 32, 32, int32)
+VFP_CONV_FIX(uh, s, 32, 32, uint16)
+VFP_CONV_FIX(ul, s, 32, 32, uint32)
#undef VFP_CONV_FIX
/* Half precision conversions. */
--
1.8.5
- [Qemu-devel] [PULL 70/76] target-arm: Rename A32 VFP conversion helpers, (continued)
- [Qemu-devel] [PULL 70/76] target-arm: Rename A32 VFP conversion helpers, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 66/76] softfloat: Add float16 <=> float64 conversion functions, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 68/76] softfloat: Add support for ties-away rounding, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 61/76] softfloat: Fix float64_to_uint64_round_to_zero, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 73/76] target-arm: A64: Add floating-point<->fixed-point instructions, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 59/76] softfloat: Fix factor 2 error for scalbn on denormal inputs, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 72/76] target-arm: A64: Add extra VFP fixed point conversion helpers, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 60/76] softfloat: Add float32_to_uint64(), Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 76/76] target-arm: A64: Add support for FCVT between half, single and double, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 51/76] arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 69/76] target-arm: Prepare VFP_CONV_FIX helpers for A64 uses,
Peter Maydell <=
- [Qemu-devel] [PULL 54/76] softfloat: Add float to 16bit integer conversions., Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 49/76] arm/xilinx_zynq: Always instantiate the GEMs, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 62/76] softfloat: Fix float64_to_uint32, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 63/76] softfloat: Fix float64_to_uint32_round_to_zero, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 47/76] target-arm: use c13_context field for CONTEXTIDR, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 64/76] softfloat: Provide complete set of accessors for fp state, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 20/76] target-arm: Widen exclusive-access support struct fields to 64 bits, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 48/76] target-arm: remove raw_read|write duplication, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 19/76] target-arm: aarch64: add support for ld lit, Peter Maydell, 2014/01/07
- [Qemu-devel] [PULL 23/76] linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext, Peter Maydell, 2014/01/07