[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [V6 PATCH 17/18] target-ppc: Scalar Round to Single Precisi
From: |
Tom Musta |
Subject: |
[Qemu-devel] [V6 PATCH 17/18] target-ppc: Scalar Round to Single Precision |
Date: |
Fri, 10 Jan 2014 13:08:01 -0600 |
This patch adds the VSX Scalar Round to Single Precision (xsrsp)
instruction.
Signed-off-by: Tom Musta <address@hidden>
---
V6: New.
target-ppc/fpu_helper.c | 17 +++++++++++++++++
target-ppc/helper.h | 1 +
target-ppc/translate.c | 2 ++
3 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 1dfb3c0..c1524e3 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2666,3 +2666,20 @@ VSX_ROUND(xvrspic, 4, float32, f32, FLOAT_ROUND_CURRENT,
0)
VSX_ROUND(xvrspim, 4, float32, f32, float_round_down, 0)
VSX_ROUND(xvrspip, 4, float32, f32, float_round_up, 0)
VSX_ROUND(xvrspiz, 4, float32, f32, float_round_to_zero, 0)
+
+void helper_xsrsp(CPUPPCState *env, uint32_t opcode)
+{
+ ppc_vsr_t xt, xb;
+
+ getVSR(xB(opcode), &xb, env);
+ getVSR(xT(opcode), &xt, env);
+
+ helper_reset_fpstatus(env);
+
+ xt.f64[0] = helper_frsp(env, xb.f64[0]);
+
+ helper_compute_fprf(env, xt.f64[0], 1);
+
+ putVSR(xT(opcode), &xt, env);
+ helper_float_check_status(env);
+}
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 6250eba..300e194 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -293,6 +293,7 @@ DEF_HELPER_2(xssubsp, void, env, i32)
DEF_HELPER_2(xsmulsp, void, env, i32)
DEF_HELPER_2(xsdivsp, void, env, i32)
DEF_HELPER_2(xsresp, void, env, i32)
+DEF_HELPER_2(xsrsp, void, env, i32)
DEF_HELPER_2(xssqrtsp, void, env, i32)
DEF_HELPER_2(xsrsqrtesp, void, env, i32)
DEF_HELPER_2(xsmaddasp, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7f2a66f..48b93c8 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7426,6 +7426,7 @@ GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
@@ -10263,6 +10264,7 @@ GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
+GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
--
1.7.1
- [Qemu-devel] [V6 PATCH 08/18] target-ppc: VSX Stage 4: Add xsdivsp, (continued)
- [Qemu-devel] [V6 PATCH 08/18] target-ppc: VSX Stage 4: Add xsdivsp, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 09/18] target-ppc: VSX Stage 4: Add xsresp, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 10/18] target-ppc: VSX Stage 4: Add xssqrtsp, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 11/18] target-ppc: VSX Stage 4: add xsrsqrtesp, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 15/18] target-ppc: Move To/From VSR Instructions, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 16/18] target-ppc: Floating Merge Word Instructions, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 17/18] target-ppc: Scalar Round to Single Precision,
Tom Musta <=
- [Qemu-devel] [V6 PATCH 18/18] target-ppc: Scalar Non-Signalling Conversions, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 13/18] target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 12/18] target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds, Tom Musta, 2014/01/10
- [Qemu-devel] [V6 PATCH 14/18] target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc, Tom Musta, 2014/01/10