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Re: [Qemu-devel] [PATCH 6/8] target-arm: A64: Add integer ops from SIMD
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH 6/8] target-arm: A64: Add integer ops from SIMD 3-same group |
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Date: |
Tue, 21 Jan 2014 11:40:02 -0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 |
On 01/17/2014 10:44 AM, Peter Maydell wrote:
> + switch (opcode) {
> + case 0x6: /* CMGT, CMHI */
> + {
> + NeonGenFn *ceqtstfns[3][2] = {
...
> + case 0x7: /* CMGE, CMHS */
> + {
> + NeonGenFn *ceqtstfns[3][2] = {
...
> + case 0x11: /* CMTST, CMEQ */
> + {
> + NeonGenFn *ceqtstfns[3][2] = {
Oh, and cut and paste on those names? Perhaps it would be less confusing to
just name them all "fns" and let the specific code block imply the rest?
r~
Re: [Qemu-devel] [PATCH 6/8] target-arm: A64: Add integer ops from SIMD 3-same group,
Richard Henderson <=
[Qemu-devel] [PATCH 4/8] target-arm: A64: Add top level decode for SIMD 3-same group, Peter Maydell, 2014/01/17
[Qemu-devel] [PATCH 3/8] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops, Peter Maydell, 2014/01/17
[Qemu-devel] [PATCH 2/8] target-arm: A64: Add SIMD three-different ABDL instructions, Peter Maydell, 2014/01/17
[Qemu-devel] [PATCH 5/8] target-arm: A64: Add logic ops from SIMD 3 same group, Peter Maydell, 2014/01/17
[Qemu-devel] [PATCH 7/8] target-arm: A64: Add simple SIMD 3-same floating point ops, Peter Maydell, 2014/01/17
Re: [Qemu-devel] [PATCH 0/8] target-arm: A64 Neon instructions, set 2, Richard Henderson, 2014/01/21