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[Qemu-devel] [PATCH 10/24] target-arm: Implement AArch64 MIDR_EL1
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 10/24] target-arm: Implement AArch64 MIDR_EL1 |
Date: |
Tue, 21 Jan 2014 20:12:16 +0000 |
Implement the AArch64 view of the MIDR system register
(for AArch64 it is a simple constant, unlike the complicated
mess that TI925 imposes on the 32-bit view).
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9a15b48..51b71a4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1800,6 +1800,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
.type = ARM_CP_OVERRIDE },
+ { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0,
+ .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST },
{ .name = "CTR",
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
--
1.8.5
- [Qemu-devel] [PATCH 00/24] target-arm: implement some AArch64 system registers, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 18/24] target-arm: Implement AArch64 VBAR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 11/24] target-arm: Implement AArch64 DAIF system register, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 16/24] target-arm: Implement AArch64 SCTLR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 10/24] target-arm: Implement AArch64 MIDR_EL1,
Peter Maydell <=
- [Qemu-devel] [PATCH 06/24] target-arm: A64: Implement store-exclusive for system mode, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 03/24] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 12/24] target-arm: Implement AArch64 cache invalidate/clean ops, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 09/24] target-arm: Implement AArch64 CurrentEL sysreg, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 23/24] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 22/24] target-arm: Implement AArch64 ID and feature registers, Peter Maydell, 2014/01/21