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[Qemu-devel] [PATCH 12/24] target-arm: Implement AArch64 cache invalidat
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 12/24] target-arm: Implement AArch64 cache invalidate/clean ops |
Date: |
Tue, 21 Jan 2014 20:12:18 +0000 |
Implement all the AArch64 cache invalidate and clean ops
(which are all NOPs since QEMU doesn't emulate the cache).
The only remaining unimplemented cache op is DC ZVA.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f23b500..d6b69dc 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1611,6 +1611,18 @@ static int aa64_daif_write(CPUARMState *env, const
ARMCPRegInfo *ri,
return 0;
}
+static int aa64_cacheop_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
+ * SCTLR_EL1.UCI is set.
+ */
+ if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
+ return EXCP_UDEF;
+ }
+ return 0;
+}
+
static const ARMCPRegInfo v8_cp_reginfo[] = {
/* Minimal set of EL0-visible registers. This will need to be expanded
* significantly for system emulation of AArch64 CPUs.
@@ -1638,6 +1650,41 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
.access = PL1_R, .type = ARM_CP_CURRENTEL },
+ /* Cache ops: all NOPs since we don't emulate caches */
+ { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
+ .access = PL1_W, .type = ARM_CP_NOP },
+ { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
+ .access = PL1_W, .type = ARM_CP_NOP },
+ { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
+ .access = PL0_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = aa64_cacheop_write },
+ { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
+ .access = PL1_W, .type = ARM_CP_NOP },
+ { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
+ .access = PL1_W, .type = ARM_CP_NOP },
+ { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
+ .access = PL0_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = aa64_cacheop_write },
+ { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
+ .access = PL1_W, .type = ARM_CP_NOP },
+ { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
+ .access = PL0_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = aa64_cacheop_write },
+ { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
+ .access = PL0_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = aa64_cacheop_write },
+ { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
+ .access = PL1_W, .type = ARM_CP_NOP },
REGINFO_SENTINEL
};
--
1.8.5
- [Qemu-devel] [PATCH 18/24] target-arm: Implement AArch64 VBAR_EL1, (continued)
- [Qemu-devel] [PATCH 18/24] target-arm: Implement AArch64 VBAR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 11/24] target-arm: Implement AArch64 DAIF system register, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 16/24] target-arm: Implement AArch64 SCTLR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 10/24] target-arm: Implement AArch64 MIDR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 06/24] target-arm: A64: Implement store-exclusive for system mode, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 03/24] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 12/24] target-arm: Implement AArch64 cache invalidate/clean ops,
Peter Maydell <=
- [Qemu-devel] [PATCH 09/24] target-arm: Implement AArch64 CurrentEL sysreg, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 23/24] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 22/24] target-arm: Implement AArch64 ID and feature registers, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 02/24] target-arm: Define names for SCTLR bits, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 08/24] target-arm: A64: Implement MSR (immediate) instructions, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 24/24] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 20/24] target-arm: Implement AArch64 MPIDR, Peter Maydell, 2014/01/21