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Re: [Qemu-devel] [PATCH 01/24] target-arm/kvm-consts.h: Define QEMU cons
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 01/24] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs |
Date: |
Thu, 23 Jan 2014 12:04:16 +0000 |
On 21 January 2014 20:12, Peter Maydell <address@hidden> wrote:
> -#ifndef TARGET_AARCH64
> +#ifdef TARGET_AARCH64
> +MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_ARM_V8)
It's been pointed out that there's a typo here which means
this won't build on AArch64 hosts: it should read
'KVM_ARM_TARGET_AEM_V8'...
thanks
-- PMM
- [Qemu-devel] [PATCH 13/24] target-arm: Implement AArch64 TLB invalidate ops, (continued)
- [Qemu-devel] [PATCH 13/24] target-arm: Implement AArch64 TLB invalidate ops, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 17/24] target-arm: Implement AArch64 TCR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 04/24] target-arm: Log bad system register accesses with LOG_UNIMP, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 19/24] target-arm: Implement AArch64 TTBR*, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 21/24] target-arm: Implement AArch64 generic timers, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 14/24] target-arm: Implement AArch64 dummy MDSCR_EL1, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 07/24] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 15/24] target-arm: Implement AArch64 memory attribute registers, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 05/24] target-arm: Add exception level to the AArch64 TB flags, Peter Maydell, 2014/01/21
- [Qemu-devel] [PATCH 01/24] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs, Peter Maydell, 2014/01/21
- Re: [Qemu-devel] [PATCH 01/24] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs,
Peter Maydell <=