Re: [Qemu-devel] [PATCH 20/24] target-arm: Implement AArch64 MPIDR

[Peter Crosthwaite]

On Wed, Jan 22, 2014 at 6:12 AM, Peter Maydell <address@hidden> wrote:
> Implement the AArch64 MPIDR system register.
>
> Signed-off-by: Peter Maydell <address@hidden>

Reviewed-by: Peter Crosthwaite <address@hidden>

> ---
>  target-arm/helper.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 1f1dec1..ef74d10 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1499,7 +1499,8 @@ static int mpidr_read(CPUARMState *env, const 
> ARMCPRegInfo *ri,
>  {
>      CPUState *cs = CPU(arm_env_get_cpu(env));
>      uint32_t mpidr = cs->cpu_index;
> -    /* We don't support setting cluster ID ([8..11])
> +    /* We don't support setting cluster ID ([8..11]) (known as Aff1
> +     * in later ARM ARM versions), or any of the higher affinity level 
> fields,
>       * so these bits always RAZ.
>       */
>      if (arm_feature(env, ARM_FEATURE_V7MP)) {
> @@ -1515,7 +1516,8 @@ static int mpidr_read(CPUARMState *env, const 
> ARMCPRegInfo *ri,
>  }
>
>  static const ARMCPRegInfo mpidr_cp_reginfo[] = {
> -    { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
> +    { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
>        .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
>      REGINFO_SENTINEL
>  };
> --
> 1.8.5
>
>