Re: [Qemu-devel] [PATCH 19/24] target-arm: Implement AArch64 TTBR*

[Peter Maydell]

On 28 January 2014 02:07, Peter Crosthwaite
<address@hidden> wrote:
> On Sat, Jan 25, 2014 at 10:09 AM, Peter Maydell
> <address@hidden> wrote:
>> On 24 January 2014 23:44, Peter Crosthwaite
>> <address@hidden> wrote:
>>> On Wed, Jan 22, 2014 at 6:12 AM, Peter Maydell <address@hidden> wrote:
>>>> +static int vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
>>>> +                             uint64_t value)
>>>> +{
>>>> +    /* 64 bit accesses to the TTBRs can change the ASID and so we
>>>> +     * must flush the TLB.
>>>> +     */
>>>> +    if ((ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT)) {
>>>> +        tlb_flush(env, 1);
>>>> +    }
>>>
>>> With the level of complexity this if has reached, is it better to just
>>> check for this ASID change rather than make this overly conservative
>>> flush?
>>
>> Adding an "is the ASID the same" would make the check more complicated
>> again. Maybe we should do it but I'd rather keep that separate from the
>> "handle 64 bit formats" patches.
>>
>
> Seems similar compexity to me.

Well, you'd need all the checks we have here, plus another condition
for the ASID match:

  if (((ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT))
       && (value & some_mask != old_value & some_mask)) {
        tlb_flush(env, 1);
   }

thanks
-- PMM