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[Qemu-devel] [PATCH v2 06/11] target-arm: Add support for AArch32 SIMD V
From: |
Will Newton |
Subject: |
[Qemu-devel] [PATCH v2 06/11] target-arm: Add support for AArch32 SIMD VRINTX |
Date: |
Tue, 28 Jan 2014 11:22:30 +0000 |
Add support for the AArch32 Advanced SIMD VRINTX instruction.
Signed-off-by: Will Newton <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
---
target-arm/translate.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 9eb5b92..c179817 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4709,6 +4709,7 @@ static const uint8_t neon_3r_sizes[] = {
#define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
#define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
#define NEON_2RM_VSHLL 38
+#define NEON_2RM_VRINTX 41
#define NEON_2RM_VCVT_F16_F32 44
#define NEON_2RM_VCVT_F32_F16 46
#define NEON_2RM_VRECPE 56
@@ -4724,7 +4725,7 @@ static int neon_2rm_is_float_op(int op)
{
/* Return true if this neon 2reg-misc op is float-to-float */
return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F ||
- op >= NEON_2RM_VRECPE_F);
+ op == NEON_2RM_VRINTX || op >= NEON_2RM_VRECPE_F);
}
/* Each entry in this array has bit n set if the insn allows
@@ -4768,6 +4769,7 @@ static const uint8_t neon_2rm_sizes[] = {
[NEON_2RM_VMOVN] = 0x7,
[NEON_2RM_VQMOVN] = 0x7,
[NEON_2RM_VSHLL] = 0x7,
+ [NEON_2RM_VRINTX] = 0x4,
[NEON_2RM_VCVT_F16_F32] = 0x2,
[NEON_2RM_VCVT_F32_F16] = 0x2,
[NEON_2RM_VRECPE] = 0x4,
@@ -6480,6 +6482,13 @@ static int disas_neon_data_insn(CPUARMState * env,
DisasContext *s, uint32_t ins
}
neon_store_reg(rm, pass, tmp2);
break;
+ case NEON_2RM_VRINTX:
+ {
+ TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+ gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpstatus);
+ tcg_temp_free_ptr(fpstatus);
+ break;
+ }
case NEON_2RM_VRECPE:
gen_helper_recpe_u32(tmp, tmp, cpu_env);
break;
--
1.8.1.4
- [Qemu-devel] [PATCH v2 01/11] target-arm: Move arm_rmode_to_sf to a shared location., Will Newton, 2014/01/28
- [Qemu-devel] [PATCH v2 02/11] target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM, Will Newton, 2014/01/28
- [Qemu-devel] [PATCH v2 03/11] target-arm: Add support for AArch32 FP VRINTR, Will Newton, 2014/01/28
- [Qemu-devel] [PATCH v2 04/11] target-arm: Add support for AArch32 FP VRINTZ, Will Newton, 2014/01/28
- [Qemu-devel] [PATCH v2 05/11] target-arm: Add support for AArch32 FP VRINTX, Will Newton, 2014/01/28
- [Qemu-devel] [PATCH v2 06/11] target-arm: Add support for AArch32 SIMD VRINTX,
Will Newton <=
- [Qemu-devel] [PATCH v2 07/11] target-arm: Add set_neon_rmode helper, Will Newton, 2014/01/28
- [Qemu-devel] [PATCH v2 09/11] target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM, Will Newton, 2014/01/28
- [Qemu-devel] [PATCH v2 08/11] target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ, Will Newton, 2014/01/28
- [Qemu-devel] [PATCH v2 10/11] target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM, Will Newton, 2014/01/28
- [Qemu-devel] [PATCH v2 11/11] target-arm: Add support for AArch32 64bit VCVTB and VCVTT, Will Newton, 2014/01/28
- Re: [Qemu-devel] [PATCH v2 01/11] target-arm: Move arm_rmode_to_sf to a shared location., Peter Maydell, 2014/01/28