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Re: [Qemu-devel] [PATCH 09/21] target-arm: A64: Implement SIMD 3-reg-sam


From: Richard Henderson
Subject: Re: [Qemu-devel] [PATCH 09/21] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns
Date: Tue, 28 Jan 2014 09:05:24 -0800
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0

On 01/26/2014 11:25 AM, Peter Maydell wrote:
> Implement the SIMD 3-reg-same instructions SQADD, UQADD,
> SQSUB, UQSUB, SSHL, USHL, SQSHl, UQSHL, SRSHL, URSHL,
> SQRSHL, UQRSHL; these are all simple calls to existing
> Neon helpers. We also enable SSHL, USHL, SRSHL and URSHL
> for the 3-reg-same-scalar category (but not the others
> because they can have non-size-64 operands and the
> scalar_3reg_same function doesn't support that yet.)
> 
> Signed-off-by: Peter Maydell <address@hidden>
> ---
>  target-arm/translate-a64.c | 134 
> +++++++++++++++++++++++++++++++++++++--------
>  1 file changed, 112 insertions(+), 22 deletions(-)

Reviewed-by: Richard Henderson <address@hidden>


r~



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