Re: [Qemu-devel] [PATCH 11/21] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD

[Richard Henderson]

On 01/26/2014 11:25 AM, Peter Maydell wrote:
> +/* Helper functions for pairwise 32 bit comparisons */
> +static void gen_pmax_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
> +{
> +    tcg_gen_movcond_i32(TCG_COND_GE, res, op1, op2, op1, op2);
> +}
> +
> +static void gen_pmax_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
> +{
> +    tcg_gen_movcond_i32(TCG_COND_GEU, res, op1, op2, op1, op2);
> +}
> +
> +static void gen_pmin_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
> +{
> +    tcg_gen_movcond_i32(TCG_COND_LE, res, op1, op2, op1, op2);
> +}
> +
> +static void gen_pmin_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
> +{
> +    tcg_gen_movcond_i32(TCG_COND_LEU, res, op1, op2, op1, op2);
> +}

These are exactly the sort of helpers I expected to see in the previous patch.
Thus my question re neon_{min,max}_{s,u}32.

Otherwise,

Reviewed-by: Richard Henderson <address@hidden>


r~