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[Qemu-devel] [PATCH v2 01/35] target-arm: Fix raw read and write functio


From: Peter Maydell
Subject: [Qemu-devel] [PATCH v2 01/35] target-arm: Fix raw read and write functions on AArch64 registers
Date: Fri, 31 Jan 2014 15:45:09 +0000

The raw read and write functions were using the ARM_CP_64BIT flag in
ri->type to determine whether to treat the register's state field as
uint32_t or uint64_t; however AArch64 register info structs don't use
that flag. Abstract out the "how big is the field?" test into a
function and fix it to work for AArch64 registers.

Signed-off-by: Peter Maydell <address@hidden>
---
 target-arm/cpu.c    | 2 +-
 target-arm/cpu.h    | 8 ++++++++
 target-arm/helper.c | 4 ++--
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 45ad7f0..935269c 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -60,7 +60,7 @@ static void cp_reg_reset(gpointer key, gpointer value, 
gpointer opaque)
         return;
     }
 
-    if (ri->type & ARM_CP_64BIT) {
+    if (cpreg_field_is_64bit(ri)) {
         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
     } else {
         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 383c582..7ccdbae 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -890,6 +890,14 @@ int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo 
*ri, uint64_t *value);
  */
 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
 
+/* Return true if this reginfo struct's field in the cpu state struct
+ * is 64 bits wide.
+ */
+static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
+{
+    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
+}
+
 static inline bool cp_access_ok(int current_pl,
                                 const ARMCPRegInfo *ri, int isread)
 {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ca5b000..e2cccb1 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -110,7 +110,7 @@ static int aarch64_fpu_gdb_set_reg(CPUARMState *env, 
uint8_t *buf, int reg)
 static int raw_read(CPUARMState *env, const ARMCPRegInfo *ri,
                     uint64_t *value)
 {
-    if (ri->type & ARM_CP_64BIT) {
+    if (cpreg_field_is_64bit(ri)) {
         *value = CPREG_FIELD64(env, ri);
     } else {
         *value = CPREG_FIELD32(env, ri);
@@ -121,7 +121,7 @@ static int raw_read(CPUARMState *env, const ARMCPRegInfo 
*ri,
 static int raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
                      uint64_t value)
 {
-    if (ri->type & ARM_CP_64BIT) {
+    if (cpreg_field_is_64bit(ri)) {
         CPREG_FIELD64(env, ri) = value;
     } else {
         CPREG_FIELD32(env, ri) = value;
-- 
1.8.5




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