Re: [Qemu-devel] [PATCH v2 01/35] target-arm: Fix raw read and write functions on AArch64 registers

[Rob Herring]

On 31 January 2014 09:45, Peter Maydell <address@hidden> wrote:
> The raw read and write functions were using the ARM_CP_64BIT flag in
> ri->type to determine whether to treat the register's state field as
> uint32_t or uint64_t; however AArch64 register info structs don't use
> that flag. Abstract out the "how big is the field?" test into a
> function and fix it to work for AArch64 registers.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
>  target-arm/cpu.c    | 2 +-
>  target-arm/cpu.h    | 8 ++++++++
>  target-arm/helper.c | 4 ++--
>  3 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 45ad7f0..935269c 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -60,7 +60,7 @@ static void cp_reg_reset(gpointer key, gpointer value, 
> gpointer opaque)
>          return;
>      }
>
> -    if (ri->type & ARM_CP_64BIT) {
> +    if (cpreg_field_is_64bit(ri)) {
>          CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
>      } else {
>          CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 383c582..7ccdbae 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -890,6 +890,14 @@ int arm_cp_read_zero(CPUARMState *env, const 
> ARMCPRegInfo *ri, uint64_t *value);
>   */
>  void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
>
> +/* Return true if this reginfo struct's field in the cpu state struct
> + * is 64 bits wide.
> + */
> +static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
> +{
> +    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);

Won't this fail when state is ARM_CP_STATE_BOTH? That was what I found
in testing as TTBR writes were not causing a tlb_flush.

Rob