[Qemu-devel] [PATCH v2 00/13] A64: Add Neon instructions, third set

[Peter Maydell]

This is the v2 from my 'Neon second and third sets' patch from
last week. The first 8 patches from that were all OK so have gone
into target-arm.next.

Changes v1->v2:
 * squashed fixes to patch 2 that were lurking in patch 3 back
   into patch 2
 * moved the patch 3 min/max helper functions into patch 2,
   to use them for plain max/min as well as pairwise max/min
 * patch 7: use -(test) not (!test - 1)
 * patch 12: special case REV of byte elements to use bswap;
   also fixed a shift left by a negative number (we were
   calculating revmask too early, before the invalid case was
   thrown out)

RTH: you've reviewed everything here except patch 2 (which
I felt had slightly too much churn to retain your tag for)
and patch 12 (for the REV special case code).

thanks
-- PMM

Alex Bennée (1):
  target-arm: A64: Add 2-reg-misc REV* instructions

Peter Maydell (12):
  target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns
  target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same
    insns
  target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD
  tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR
  target-arm: A64: Implement scalar pairwise ops
  target-arm: A64: Implement remaining integer scalar-3-same insns
  target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc
  target-arm: A64: Add skeleton decode for SIMD 2-reg misc group
  target-arm: A64: Implement 2-register misc compares, ABS, NEG
  target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT
  target-arm: A64: Add narrowing 2-reg-misc instructions
  target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group

 target-arm/helper.h        |    1 +
 target-arm/neon_helper.c   |   12 +
 target-arm/translate-a64.c | 1211 ++++++++++++++++++++++++++++++++++++++++----
 tcg/tcg.h                  |    3 +
 4 files changed, 1136 insertions(+), 91 deletions(-)

-- 
1.8.5