[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 00/29] target-arm queue
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 00/29] target-arm queue |
Date: |
Sat, 8 Feb 2014 15:57:35 +0000 |
Pull request for the target-arm queue...
thanks
-- PMM
The following changes since commit 3ea3bd62451ac79478b440ad9fe2a4cd69783a1f:
Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20140204-1'
into staging (2014-02-08 13:12:50 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20140208
for you to fetch changes up to 69991d7dcbcf7f3fe38274bc67fcba3cbbfda0cf:
arm/zynq: Add software system reset via SCLR (2014-02-08 14:50:48 +0000)
----------------------------------------------------------------
target-arm queue:
* more A64 Neon instructions
* AArch32 VCVTB and VCVTT ARMv8 instructions
* fixes to inaccuracies in GIC emulation
* libvixl disassembler for A64
* Allwinner SoC ethernet controller
* zynq software system reset support
----------------------------------------------------------------
Alex Bennée (1):
target-arm: A64: Add 2-reg-misc REV* instructions
Beniamino Galvani (4):
util/fifo8: implement push/pop of multiple bytes
util/fifo8: clear fifo head upon reset
hw/net: add support for Allwinner EMAC Fast Ethernet controller
hw/arm/allwinner-a10: initialize EMAC
Christoffer Dall (5):
arm_gic: Fix GIC pending behavior
arm_gic: Keep track of SGI sources
arm_gic: Support setting/getting binary point reg
vmstate: Add uint32 2D-array support
arm_gic: Add GICC_APRn state to the GICState
Claudio Fontana (1):
disas: Implement disassembly output for A64
Peter Maydell (16):
target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns
target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same
insns
target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD
tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR
target-arm: A64: Implement scalar pairwise ops
target-arm: A64: Implement remaining integer scalar-3-same insns
target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc
target-arm: A64: Add skeleton decode for SIMD 2-reg misc group
target-arm: A64: Implement 2-register misc compares, ABS, NEG
target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT
target-arm: A64: Add narrowing 2-reg-misc instructions
target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group
rules.mak: Support .cc as a C++ source file suffix
rules.mak: Link with C++ if we have a C++ compiler
disas: Add subset of libvixl sources for A64 disassembler
disas/libvixl: Fix upstream libvixl compilation issues
Sebastian Huber (1):
arm/zynq: Add software system reset via SCLR
Will Newton (1):
target-arm: Add support for AArch32 64bit VCVTB and VCVTT
configure | 4 +
default-configs/arm-softmmu.mak | 1 +
disas.c | 14 +-
disas/Makefile.objs | 5 +
disas/arm-a64.cc | 87 ++
disas/libvixl/LICENCE | 30 +
disas/libvixl/Makefile.objs | 8 +
disas/libvixl/README | 12 +
disas/libvixl/a64/assembler-a64.h | 1784 +++++++++++++++++++++++++++++++++
disas/libvixl/a64/constants-a64.h | 1104 ++++++++++++++++++++
disas/libvixl/a64/cpu-a64.h | 56 ++
disas/libvixl/a64/decoder-a64.cc | 712 +++++++++++++
disas/libvixl/a64/decoder-a64.h | 198 ++++
disas/libvixl/a64/disasm-a64.cc | 1678 +++++++++++++++++++++++++++++++
disas/libvixl/a64/disasm-a64.h | 109 ++
disas/libvixl/a64/instructions-a64.cc | 238 +++++
disas/libvixl/a64/instructions-a64.h | 344 +++++++
disas/libvixl/globals.h | 65 ++
disas/libvixl/platform.h | 43 +
disas/libvixl/utils.cc | 120 +++
disas/libvixl/utils.h | 126 +++
hw/arm/allwinner-a10.c | 16 +
hw/arm/cubieboard.c | 11 +-
hw/intc/arm_gic.c | 179 +++-
hw/intc/arm_gic_common.c | 8 +-
hw/intc/gic_internal.h | 16 +-
hw/misc/zynq_slcr.c | 5 +
hw/net/Makefile.objs | 1 +
hw/net/allwinner_emac.c | 539 ++++++++++
include/disas/bfd.h | 1 +
include/hw/arm/allwinner-a10.h | 3 +
include/hw/intc/arm_gic_common.h | 33 +
include/hw/net/allwinner_emac.h | 210 ++++
include/migration/vmstate.h | 6 +
include/qemu/fifo8.h | 61 ++
rules.mak | 14 +-
target-arm/helper.h | 1 +
target-arm/neon_helper.c | 12 +
target-arm/translate-a64.c | 1213 ++++++++++++++++++++--
target-arm/translate.c | 83 +-
tcg/tcg.h | 3 +
util/fifo8.c | 47 +
42 files changed, 9044 insertions(+), 156 deletions(-)
create mode 100644 disas/arm-a64.cc
create mode 100644 disas/libvixl/LICENCE
create mode 100644 disas/libvixl/Makefile.objs
create mode 100644 disas/libvixl/README
create mode 100644 disas/libvixl/a64/assembler-a64.h
create mode 100644 disas/libvixl/a64/constants-a64.h
create mode 100644 disas/libvixl/a64/cpu-a64.h
create mode 100644 disas/libvixl/a64/decoder-a64.cc
create mode 100644 disas/libvixl/a64/decoder-a64.h
create mode 100644 disas/libvixl/a64/disasm-a64.cc
create mode 100644 disas/libvixl/a64/disasm-a64.h
create mode 100644 disas/libvixl/a64/instructions-a64.cc
create mode 100644 disas/libvixl/a64/instructions-a64.h
create mode 100644 disas/libvixl/globals.h
create mode 100644 disas/libvixl/platform.h
create mode 100644 disas/libvixl/utils.cc
create mode 100644 disas/libvixl/utils.h
create mode 100644 hw/net/allwinner_emac.c
create mode 100644 include/hw/net/allwinner_emac.h
- [Qemu-devel] [PULL 00/29] target-arm queue,
Peter Maydell <=
- [Qemu-devel] [PULL 12/29] target-arm: A64: Add 2-reg-misc REV* instructions, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 11/29] target-arm: A64: Add narrowing 2-reg-misc instructions, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 25/29] util/fifo8: implement push/pop of multiple bytes, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 10/29] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 29/29] arm/zynq: Add software system reset via SCLR, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 16/29] arm_gic: Keep track of SGI sources, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 01/29] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 06/29] target-arm: A64: Implement remaining integer scalar-3-same insns, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 07/29] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc, Peter Maydell, 2014/02/08
- [Qemu-devel] [PULL 19/29] arm_gic: Add GICC_APRn state to the GICState, Peter Maydell, 2014/02/08