Re: [Qemu-devel] [PATCH v2 34/35] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers

[Peter Crosthwaite]

On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell <address@hidden> wrote:
> In AArch64 the breakpoint and watchpoint registers are mandatory, so the
> kernel always accesses them on bootup. Implement dummy versions, which
> read as written but have no actual effect.
>
> Signed-off-by: Peter Maydell <address@hidden>

Reviewed-by: Peter Crosthwaite <address@hidden>

> ---
>  target-arm/cpu.h    |  4 ++++
>  target-arm/helper.c | 32 ++++++++++++++++++++++++++++++++
>  2 files changed, 36 insertions(+)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 24a8e93..267d5ae 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -216,6 +216,10 @@ typedef struct CPUARMState {
>          uint32_t c15_diagnostic; /* diagnostic register */
>          uint32_t c15_power_diagnostic;
>          uint32_t c15_power_control; /* power control */
> +        uint64_t dbgbvr[16]; /* breakpoint value registers */
> +        uint64_t dbgbcr[16]; /* breakpoint control registers */
> +        uint64_t dbgwvr[16]; /* watchpoint value registers */
> +        uint64_t dbgwcr[16]; /* watchpoint control registers */
>      } cp15;
>
>      struct {
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index eb37e7e..1621030 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1787,6 +1787,37 @@ static CPAccessResult ctr_el0_access(CPUARMState *env, 
> const ARMCPRegInfo *ri)
>      return CP_ACCESS_OK;
>  }
>
> +static void define_aarch64_debug_regs(ARMCPU *cpu)
> +{
> +    /* Define breakpoint and watchpoint registers. These do nothing
> +     * but read as written, for now.
> +     */
> +    int i;
> +
> +    for (i = 0; i < 16; i++) {
> +        ARMCPRegInfo dbgregs[] = {
> +            { .name = "DBGBVR", .state = ARM_CP_STATE_AA64,
> +              .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
> +              .access = PL1_RW,
> +              .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },
> +            { .name = "DBGBCR", .state = ARM_CP_STATE_AA64,
> +              .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
> +              .access = PL1_RW,
> +              .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
> +            { .name = "DBGWVR", .state = ARM_CP_STATE_AA64,
> +              .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
> +              .access = PL1_RW,
> +              .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },
> +            { .name = "DBGWCR", .state = ARM_CP_STATE_AA64,
> +              .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
> +              .access = PL1_RW,
> +              .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },
> +               REGINFO_SENTINEL
> +        };
> +        define_arm_cp_regs(cpu, dbgregs);
> +    }
> +}
> +
>  void register_cp_regs_for_features(ARMCPU *cpu)
>  {
>      /* Register all the coprocessor registers based on feature bits */
> @@ -1928,6 +1959,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>          };
>          define_arm_cp_regs(cpu, v8_idregs);
>          define_arm_cp_regs(cpu, v8_cp_reginfo);
> +        define_aarch64_debug_regs(cpu);
>      }
>      if (arm_feature(env, ARM_FEATURE_MPU)) {
>          /* These are the MPU registers prior to PMSAv6. Any new
> --
> 1.8.5
>
>