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Re: [Qemu-devel] [PATCH 7/8] softfloat: Support halving the result of mu
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 7/8] softfloat: Support halving the result of muladd operation |
Date: |
Mon, 10 Feb 2014 21:31:52 +0000 |
On 10 February 2014 20:15, Richard Henderson <address@hidden> wrote:
> On 02/07/2014 01:49 PM, Peter Maydell wrote:
>> /* Zero plus something non-zero : just return the something */
>> + if (flags & float_muladd_halve_result) {
>> + if (cExp == 0) {
>> + shift32RightJamming(cSig, 1, &cSig);
>> + } else if (cExp == 1) {
>> + shift32RightJamming(cSig, 1, &cSig);
>> + cSig |= (1 << 22);
>> + cExp = 0;
>> + } else {
>> + cExp--;
>> + }
>
> Surely better to just use roundAndPackFloat for this case. Looks to me that
> you're missing inexact and underflow exceptions at least.
Good point.
thanks
-- PMM
- [Qemu-devel] [PATCH 0/8] A64: Neon support, fourth set, Peter Maydell, 2014/02/07
- [Qemu-devel] [PATCH 2/8] target-arm: A64: Implement long vector x indexed insns, Peter Maydell, 2014/02/07
- [Qemu-devel] [PATCH 7/8] softfloat: Support halving the result of muladd operation, Peter Maydell, 2014/02/07
- [Qemu-devel] [PATCH 8/8] target-arm: A64: Implement remaining 3-same instructions, Peter Maydell, 2014/02/07
- [Qemu-devel] [PATCH 5/8] target-arm: A64: Implement SIMD FP compare and set insns, Peter Maydell, 2014/02/07
- [Qemu-devel] [PATCH 3/8] target-arm: A64: Implement SIMD scalar indexed instructions, Peter Maydell, 2014/02/07
- [Qemu-devel] [PATCH 6/8] target-arm: A64: Implement floating point pairwise insns, Peter Maydell, 2014/02/07
- [Qemu-devel] [PATCH 1/8] target-arm: A64: Implement plain vector SIMD indexed element insns, Peter Maydell, 2014/02/07
- [Qemu-devel] [PATCH 4/8] target-arm: A64: Implement scalar three different instructions, Peter Maydell, 2014/02/07
- Re: [Qemu-devel] [PATCH 0/8] A64: Neon support, fourth set, Richard Henderson, 2014/02/10