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[Qemu-devel] [PATCH 01/28] target-ppc: Altivec 2.07: Add Instruction Fla
From: |
Tom Musta |
Subject: |
[Qemu-devel] [PATCH 01/28] target-ppc: Altivec 2.07: Add Instruction Flag |
Date: |
Wed, 12 Feb 2014 15:22:52 -0600 |
This patch adds a flag that will be used to tag the Altivec instructions
introduced in Power ISA Version 2.07.
The flag is added to Power8 model since P8 supports these instructions.
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/cpu.h | 5 ++++-
target-ppc/translate_init.c | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 214afd9..f25caf1 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1893,12 +1893,15 @@ enum {
PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
/* ISA 2.07 load/store quadword */
PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
+ /* ISA 2.07 Altivec */
+ PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
- PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207)
+ PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
+ PPC2_ALTIVEC_207)
};
/*****************************************************************************/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d7bcbba..ea805db 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7340,7 +7340,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
- PPC2_LSQ_ISA207;
+ PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207;
pcc->msr_mask = 0x800000000284FF36ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
--
1.7.1
- [Qemu-devel] [PATCH 00/28] target-ppc: Altivec 2.07, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 01/28] target-ppc: Altivec 2.07: Add Instruction Flag,
Tom Musta <=
- [Qemu-devel] [PATCH 02/28] target-ppc: Altivec 2.07: Update AVR Structure, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 03/28] target-ppc: Altivec 2.07: Add GEN_VXFORM3, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 04/28] target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 05/28] target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 06/28] target-ppc: Altivec 2.07: Add Support for R-Form Dual Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 07/28] target-ppc: Altivec 2.07: Vector Logical Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 08/28] target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 09/28] target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 10/28] target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 11/28] target-ppc: Altivec 2.07: vmuluw Instruction, Tom Musta, 2014/02/12