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[Qemu-devel] [PATCH 19/28] target-ppc: Altivec 2.07: Vector Doubleword R
From: |
Tom Musta |
Subject: |
[Qemu-devel] [PATCH 19/28] target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions |
Date: |
Wed, 12 Feb 2014 15:23:10 -0600 |
This patch adds the vector doublword rotate and shift instructions
introduced in Power ISA Version 2.07:
- Vector Rotate Left Doubleword instruction (vrld)
- Vector Shift Left Doubleword (vsld)
- Vector Shift Right Doubleword (vsrd)
- Vector Shift Right Algegbraic Doubleword (vsrad)
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/helper.h | 4 ++++
target-ppc/int_helper.c | 4 ++++
target-ppc/translate.c | 8 ++++++++
3 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 6a7e99f..3201268 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -184,12 +184,15 @@ DEF_HELPER_3(vmuluwm, void, avr, avr, avr)
DEF_HELPER_3(vsrab, void, avr, avr, avr)
DEF_HELPER_3(vsrah, void, avr, avr, avr)
DEF_HELPER_3(vsraw, void, avr, avr, avr)
+DEF_HELPER_3(vsrad, void, avr, avr, avr)
DEF_HELPER_3(vsrb, void, avr, avr, avr)
DEF_HELPER_3(vsrh, void, avr, avr, avr)
DEF_HELPER_3(vsrw, void, avr, avr, avr)
+DEF_HELPER_3(vsrd, void, avr, avr, avr)
DEF_HELPER_3(vslb, void, avr, avr, avr)
DEF_HELPER_3(vslh, void, avr, avr, avr)
DEF_HELPER_3(vslw, void, avr, avr, avr)
+DEF_HELPER_3(vsld, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
@@ -211,6 +214,7 @@ DEF_HELPER_4(vsubuws, void, env, avr, avr, avr)
DEF_HELPER_3(vrlb, void, avr, avr, avr)
DEF_HELPER_3(vrlh, void, avr, avr, avr)
DEF_HELPER_3(vrlw, void, avr, avr, avr)
+DEF_HELPER_3(vrld, void, avr, avr, avr)
DEF_HELPER_3(vsl, void, avr, avr, avr)
DEF_HELPER_3(vsr, void, avr, avr, avr)
DEF_HELPER_4(vsldoi, void, avr, avr, avr, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 59b5a1f..b4a7298 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1142,6 +1142,7 @@ VRFI(z, float_round_to_zero)
VROTATE(b, u8, 0x7)
VROTATE(h, u16, 0xF)
VROTATE(w, u32, 0x1F)
+VROTATE(d, u64, 0x3F)
#undef VROTATE
void helper_vrsqrtefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b)
@@ -1236,6 +1237,7 @@ VSHIFT(r, RIGHT)
VSL(b, u8, 0x7)
VSL(h, u16, 0x0F)
VSL(w, u32, 0x1F)
+VSL(d, u64, 0x3F)
#undef VSL
void helper_vsldoi(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
@@ -1332,9 +1334,11 @@ VSPLTI(w, s32, int32_t)
VSR(ab, s8, 0x7)
VSR(ah, s16, 0xF)
VSR(aw, s32, 0x1F)
+VSR(ad, s64, 0x3F)
VSR(b, u8, 0x7)
VSR(h, u16, 0xF)
VSR(w, u32, 0x1F)
+VSR(d, u64, 0x3F)
#undef VSR
void helper_vsro(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 4d3c73d..561d22d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7016,12 +7016,15 @@ GEN_VXFORM(vmulesw, 4, 14);
GEN_VXFORM(vslb, 2, 4);
GEN_VXFORM(vslh, 2, 5);
GEN_VXFORM(vslw, 2, 6);
+GEN_VXFORM(vsld, 2, 23);
GEN_VXFORM(vsrb, 2, 8);
GEN_VXFORM(vsrh, 2, 9);
GEN_VXFORM(vsrw, 2, 10);
+GEN_VXFORM(vsrd, 2, 27);
GEN_VXFORM(vsrab, 2, 12);
GEN_VXFORM(vsrah, 2, 13);
GEN_VXFORM(vsraw, 2, 14);
+GEN_VXFORM(vsrad, 2, 15);
GEN_VXFORM(vslo, 6, 16);
GEN_VXFORM(vsro, 6, 17);
GEN_VXFORM(vaddcuw, 0, 6);
@@ -7041,6 +7044,7 @@ GEN_VXFORM_ENV(vsubsws, 0, 30);
GEN_VXFORM(vrlb, 2, 0);
GEN_VXFORM(vrlh, 2, 1);
GEN_VXFORM(vrlw, 2, 2);
+GEN_VXFORM(vrld, 2, 3);
GEN_VXFORM(vsl, 2, 7);
GEN_VXFORM(vsr, 2, 11);
GEN_VXFORM_ENV(vpkuhum, 7, 0);
@@ -10432,12 +10436,15 @@ GEN_VXFORM_207(vmulesw, 4, 14),
GEN_VXFORM(vslb, 2, 4),
GEN_VXFORM(vslh, 2, 5),
GEN_VXFORM(vslw, 2, 6),
+GEN_VXFORM_207(vsld, 2, 23),
GEN_VXFORM(vsrb, 2, 8),
GEN_VXFORM(vsrh, 2, 9),
GEN_VXFORM(vsrw, 2, 10),
+GEN_VXFORM_207(vsrd, 2, 27),
GEN_VXFORM(vsrab, 2, 12),
GEN_VXFORM(vsrah, 2, 13),
GEN_VXFORM(vsraw, 2, 14),
+GEN_VXFORM_207(vsrad, 2, 15),
GEN_VXFORM(vslo, 6, 16),
GEN_VXFORM(vsro, 6, 17),
GEN_VXFORM(vaddcuw, 0, 6),
@@ -10457,6 +10464,7 @@ GEN_VXFORM(vsubsws, 0, 30),
GEN_VXFORM(vrlb, 2, 0),
GEN_VXFORM(vrlh, 2, 1),
GEN_VXFORM(vrlw, 2, 2),
+GEN_VXFORM_207(vrld, 2, 3),
GEN_VXFORM(vsl, 2, 7),
GEN_VXFORM(vsr, 2, 11),
GEN_VXFORM(vpkuhum, 7, 0),
--
1.7.1
- [Qemu-devel] [PATCH 09/28] target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers, (continued)
- [Qemu-devel] [PATCH 09/28] target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 10/28] target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 11/28] target-ppc: Altivec 2.07: vmuluw Instruction, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 12/28] target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 13/28] target-ppc: Altivec 2.07: Vector Population Count Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 14/28] target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 15/28] target-ppc: Altivec 2.07: Pack Doubleword Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 16/28] target-ppc: Altivec 2.07: Unpack Signed Word Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 17/28] target-ppc: Altivec 2.07: Vector Merge Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 18/28] target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and Shifts, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 19/28] target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions,
Tom Musta <=
- [Qemu-devel] [PATCH 20/28] target-ppc: Altivec 2.07: Quadword Addition and Subtracation, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 21/28] target-ppc: Altivec 2.07: vbpermq Instruction, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 22/28] target-ppc: Altivec 2.07: Doubleword Compares, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 23/28] target-ppc: Altivec 2.07: Vector Gather Bits by Bytes, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 24/28] target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 25/28] target-ppc: Altivec 2.07: Binary Coded Decimal Instructions, Tom Musta, 2014/02/12
- [Qemu-devel] [PATCH 26/28] target-ppc: Altivec 2.07: AES Instructions, Tom Musta, 2014/02/12