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[Qemu-devel] [PATCH v3 13/31] target-arm: Implement AArch64 MPIDR
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v3 13/31] target-arm: Implement AArch64 MPIDR |
Date: |
Sat, 15 Feb 2014 16:07:06 +0000 |
Implement the AArch64 MPIDR system register.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/helper.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f5d9d2f..c81e73f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1435,7 +1435,8 @@ static uint64_t mpidr_read(CPUARMState *env, const
ARMCPRegInfo *ri)
{
CPUState *cs = CPU(arm_env_get_cpu(env));
uint32_t mpidr = cs->cpu_index;
- /* We don't support setting cluster ID ([8..11])
+ /* We don't support setting cluster ID ([8..11]) (known as Aff1
+ * in later ARM ARM versions), or any of the higher affinity level fields,
* so these bits always RAZ.
*/
if (arm_feature(env, ARM_FEATURE_V7MP)) {
@@ -1450,7 +1451,8 @@ static uint64_t mpidr_read(CPUARMState *env, const
ARMCPRegInfo *ri)
}
static const ARMCPRegInfo mpidr_cp_reginfo[] = {
- { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
+ { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
.access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
REGINFO_SENTINEL
};
--
1.8.5
- [Qemu-devel] [PATCH v3 00/31] A64 system emulation prequisites, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 07/31] target-arm: Implement AArch64 dummy MDSCR_EL1, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 21/31] target-arm: Implement AArch64 DAIF system register, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 29/31] target-arm: A64: Add assertion that FP access was checked, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 13/31] target-arm: Implement AArch64 MPIDR,
Peter Maydell <=
- [Qemu-devel] [PATCH v3 19/31] target-arm: A64: Implement WFI, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 11/31] target-arm: Implement AArch64 VBAR_EL1, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 20/31] target-arm: Store AIF bits in env->pstate for AArch32, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 09/31] target-arm: Implement AArch64 SCTLR_EL1, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 10/31] target-arm: Implement AArch64 TCR_EL1, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 12/31] target-arm: Implement AArch64 TTBR*, Peter Maydell, 2014/02/15