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[Qemu-devel] [PATCH 1/2] target-xtensa: refactor standard core configura
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 1/2] target-xtensa: refactor standard core configuration |
Date: |
Sat, 15 Feb 2014 21:30:56 +0400 |
Coalesce all standard configuration sections into single
DEFAULT_SECTIONS macro for all cores. This allows to add new features in
a single place: overlay_tool.h
Signed-off-by: Max Filippov <address@hidden>
---
target-xtensa/core-dc232b.c | 8 +-------
target-xtensa/core-dc233c.c | 8 +-------
target-xtensa/core-fsf.c | 8 +-------
target-xtensa/overlay_tool.h | 10 ++++++++++
4 files changed, 13 insertions(+), 21 deletions(-)
diff --git a/target-xtensa/core-dc232b.c b/target-xtensa/core-dc232b.c
index 0bfcf24..c51e11e 100644
--- a/target-xtensa/core-dc232b.c
+++ b/target-xtensa/core-dc232b.c
@@ -35,7 +35,6 @@
static const XtensaConfig dc232b = {
.name = "dc232b",
- .options = XTENSA_OPTIONS,
.gdb_regmap = {
.num_regs = 120,
.num_core_regs = 52,
@@ -43,13 +42,8 @@ static const XtensaConfig dc232b = {
#include "core-dc232b/gdb-config.c"
}
},
- .nareg = XCHAL_NUM_AREGS,
- .ndepc = 1,
- EXCEPTIONS_SECTION,
- INTERRUPTS_SECTION,
- TLB_SECTION,
- DEBUG_SECTION,
.clock_freq_khz = 10000,
+ DEFAULT_SECTIONS
};
REGISTER_CORE(dc232b)
diff --git a/target-xtensa/core-dc233c.c b/target-xtensa/core-dc233c.c
index 738d543..42dd64f 100644
--- a/target-xtensa/core-dc233c.c
+++ b/target-xtensa/core-dc233c.c
@@ -36,7 +36,6 @@
static const XtensaConfig dc233c = {
.name = "dc233c",
- .options = XTENSA_OPTIONS,
.gdb_regmap = {
.num_regs = 121,
.num_core_regs = 52,
@@ -44,13 +43,8 @@ static const XtensaConfig dc233c = {
#include "core-dc233c/gdb-config.c"
}
},
- .nareg = XCHAL_NUM_AREGS,
- .ndepc = 1,
- EXCEPTIONS_SECTION,
- INTERRUPTS_SECTION,
- TLB_SECTION,
- DEBUG_SECTION,
.clock_freq_khz = 10000,
+ DEFAULT_SECTIONS
};
REGISTER_CORE(dc233c)
diff --git a/target-xtensa/core-fsf.c b/target-xtensa/core-fsf.c
index d4660ed..6859bee 100644
--- a/target-xtensa/core-fsf.c
+++ b/target-xtensa/core-fsf.c
@@ -35,15 +35,9 @@
static const XtensaConfig fsf = {
.name = "fsf",
- .options = XTENSA_OPTIONS,
/* GDB for this core is not supported currently */
- .nareg = XCHAL_NUM_AREGS,
- .ndepc = 1,
- EXCEPTIONS_SECTION,
- INTERRUPTS_SECTION,
- TLB_SECTION,
- DEBUG_SECTION,
.clock_freq_khz = 10000,
+ DEFAULT_SECTIONS
};
REGISTER_CORE(fsf)
diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h
index 2b4443d..25b7970 100644
--- a/target-xtensa/overlay_tool.h
+++ b/target-xtensa/overlay_tool.h
@@ -320,6 +320,16 @@
.nibreak = XCHAL_NUM_IBREAK, \
.ndbreak = XCHAL_NUM_DBREAK
+#define DEFAULT_SECTIONS \
+ .options = XTENSA_OPTIONS, \
+ .nareg = XCHAL_NUM_AREGS, \
+ .ndepc = (XCHAL_XEA_VERSION >= 2), \
+ EXCEPTIONS_SECTION, \
+ INTERRUPTS_SECTION, \
+ TLB_SECTION, \
+ DEBUG_SECTION
+
+
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0
#endif
--
1.8.1.4