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[Qemu-devel] [PULL 04/15] tcg/optimize: fix known-zero bits optimization
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 04/15] tcg/optimize: fix known-zero bits optimization |
Date: |
Mon, 17 Feb 2014 19:15:54 -0600 |
From: Aurelien Jarno <address@hidden>
Known-zero bits optimization is a great idea that helps to generate more
optimized code. However the current implementation only works in very few
cases as the computed mask is not saved.
Fix this to make it really working.
Reviewed-by: Paolo Bonzini <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/optimize.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index c5cdde2..7838be2 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -691,7 +691,8 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t
*tcg_opc_ptr,
break;
}
- /* Simplify using known-zero bits */
+ /* Simplify using known-zero bits. Currently only ops with a single
+ output argument is supported. */
mask = -1;
affected = -1;
switch (op) {
@@ -1149,6 +1150,11 @@ static TCGArg *tcg_constant_folding(TCGContext *s,
uint16_t *tcg_opc_ptr,
} else {
for (i = 0; i < def->nb_oargs; i++) {
reset_temp(args[i]);
+ /* Save the corresponding known-zero bits mask for the
+ first output argument (only one supported so far). */
+ if (i == 0) {
+ temps[args[i]].mask = mask;
+ }
}
}
for (i = 0; i < def->nb_args; i++) {
--
1.8.5.3
- [Qemu-devel] [PULL 00/15] tcg updates, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 02/15] tcg-arm: The shift count of op_rotl_i32 is in args[2] not args[1]., Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 01/15] TCG: Fix 32-bit host allocation typo, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 03/15] tcg/optimize: fix known-zero bits for right shift ops, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 04/15] tcg/optimize: fix known-zero bits optimization,
Richard Henderson <=
- [Qemu-devel] [PULL 05/15] tcg/optimize: improve known-zero bits for 32-bit ops, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 06/15] tcg/optimize: add known-zero bits compute for load ops, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 07/15] tcg/optimize: Handle known-zeros masks for ANDC, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 08/15] tcg/optimize: Simply some logical ops to NOT, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 09/15] tcg/optimize: Optmize ANDC X, Y, Y to MOV X, 0, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 10/15] tcg/optimize: Add more identity simplifications, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 11/15] disas/i386: Disassemble ANDN/SHLX/SHRX/SHAX, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 12/15] tcg/i386: Move TCG_CT_CONST_* to tcg-target.c, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 13/15] tcg/i386: Add tcg_out_vex_modrm, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 15/15] tcg/i386: Use SHLX/SHRX/SARX instructions, Richard Henderson, 2014/02/17