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[Qemu-devel] [PULL 08/15] tcg/optimize: Simply some logical ops to NOT
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 08/15] tcg/optimize: Simply some logical ops to NOT |
Date: |
Mon, 17 Feb 2014 19:15:58 -0600 |
Given, of course, an appropriate constant. These could be generated
from the "canonical" operation for inversion on the guest, or via
other optimizations.
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/optimize.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 4bea8a5..0b1dd13 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -655,6 +655,63 @@ static TCGArg *tcg_constant_folding(TCGContext *s,
uint16_t *tcg_opc_ptr,
}
}
break;
+ CASE_OP_32_64(xor):
+ CASE_OP_32_64(nand):
+ if (temps[args[1]].state != TCG_TEMP_CONST
+ && temps[args[2]].state == TCG_TEMP_CONST
+ && temps[args[2]].val == -1) {
+ i = 1;
+ goto try_not;
+ }
+ break;
+ CASE_OP_32_64(nor):
+ if (temps[args[1]].state != TCG_TEMP_CONST
+ && temps[args[2]].state == TCG_TEMP_CONST
+ && temps[args[2]].val == 0) {
+ i = 1;
+ goto try_not;
+ }
+ break;
+ CASE_OP_32_64(andc):
+ if (temps[args[2]].state != TCG_TEMP_CONST
+ && temps[args[1]].state == TCG_TEMP_CONST
+ && temps[args[1]].val == -1) {
+ i = 2;
+ goto try_not;
+ }
+ break;
+ CASE_OP_32_64(orc):
+ CASE_OP_32_64(eqv):
+ if (temps[args[2]].state != TCG_TEMP_CONST
+ && temps[args[1]].state == TCG_TEMP_CONST
+ && temps[args[1]].val == 0) {
+ i = 2;
+ goto try_not;
+ }
+ break;
+ try_not:
+ {
+ TCGOpcode not_op;
+ bool have_not;
+
+ if (def->flags & TCG_OPF_64BIT) {
+ not_op = INDEX_op_not_i64;
+ have_not = TCG_TARGET_HAS_not_i64;
+ } else {
+ not_op = INDEX_op_not_i32;
+ have_not = TCG_TARGET_HAS_not_i32;
+ }
+ if (!have_not) {
+ break;
+ }
+ s->gen_opc_buf[op_index] = not_op;
+ reset_temp(args[0]);
+ gen_args[0] = args[0];
+ gen_args[1] = args[i];
+ args += 3;
+ gen_args += 2;
+ continue;
+ }
default:
break;
}
--
1.8.5.3
- [Qemu-devel] [PULL 00/15] tcg updates, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 02/15] tcg-arm: The shift count of op_rotl_i32 is in args[2] not args[1]., Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 01/15] TCG: Fix 32-bit host allocation typo, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 03/15] tcg/optimize: fix known-zero bits for right shift ops, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 04/15] tcg/optimize: fix known-zero bits optimization, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 05/15] tcg/optimize: improve known-zero bits for 32-bit ops, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 06/15] tcg/optimize: add known-zero bits compute for load ops, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 07/15] tcg/optimize: Handle known-zeros masks for ANDC, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 08/15] tcg/optimize: Simply some logical ops to NOT,
Richard Henderson <=
- [Qemu-devel] [PULL 09/15] tcg/optimize: Optmize ANDC X, Y, Y to MOV X, 0, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 10/15] tcg/optimize: Add more identity simplifications, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 11/15] disas/i386: Disassemble ANDN/SHLX/SHRX/SHAX, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 12/15] tcg/i386: Move TCG_CT_CONST_* to tcg-target.c, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 13/15] tcg/i386: Add tcg_out_vex_modrm, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 15/15] tcg/i386: Use SHLX/SHRX/SARX instructions, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 14/15] tcg/i386: Use ANDN instruction, Richard Henderson, 2014/02/17
- Re: [Qemu-devel] [PULL 00/15] tcg updates, Kevin Wolf, 2014/02/19