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[Qemu-devel] [PULL 13/15] tcg/i386: Add tcg_out_vex_modrm
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 13/15] tcg/i386: Add tcg_out_vex_modrm |
Date: |
Mon, 17 Feb 2014 19:16:03 -0600 |
Prepare for emitting BMI insns which require VEX encoding.
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/i386/tcg-target.c | 41 ++++++++++++++++++++++++++++++++++++++---
1 file changed, 38 insertions(+), 3 deletions(-)
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index 7008b0e..00dbc3b 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -402,9 +402,9 @@ static void tcg_out_opc(TCGContext *s, int opc, int r, int
rm, int x)
rex = 0;
rex |= (opc & P_REXW) ? 0x8 : 0x0; /* REX.W */
- rex |= (r & 8) >> 1; /* REX.R */
- rex |= (x & 8) >> 2; /* REX.X */
- rex |= (rm & 8) >> 3; /* REX.B */
+ rex |= (r & 8) >> 1; /* REX.R */
+ rex |= (x & 8) >> 2; /* REX.X */
+ rex |= (rm & 8) >> 3; /* REX.B */
/* P_REXB_{R,RM} indicates that the given register is the low byte.
For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do,
@@ -453,6 +453,41 @@ static void tcg_out_modrm(TCGContext *s, int opc, int r,
int rm)
tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
}
+static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
+{
+ int tmp;
+
+ if ((opc & (P_REXW | P_EXT | P_EXT38)) || (rm & 8)) {
+ /* Three byte VEX prefix. */
+ tcg_out8(s, 0xc4);
+
+ /* VEX.m-mmmm */
+ if (opc & P_EXT38) {
+ tmp = 2;
+ } else if (opc & P_EXT) {
+ tmp = 1;
+ } else {
+ tcg_abort();
+ }
+ tmp |= 0x40; /* VEX.X */
+ tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */
+ tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */
+ tcg_out8(s, tmp);
+
+ tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */
+ } else {
+ /* Two byte VEX prefix. */
+ tcg_out8(s, 0xc5);
+
+ tmp = (r & 8 ? 0 : 0x80); /* VEX.R */
+ }
+ tmp |= (opc & P_DATA16 ? 1 : 0); /* VEX.pp */
+ tmp |= (~v & 15) << 3; /* VEX.vvvv */
+ tcg_out8(s, tmp);
+ tcg_out8(s, opc);
+ tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
+}
+
/* Output an opcode with a full "rm + (index<<shift) + offset" address mode.
We handle either RM and INDEX missing with a negative value. In 64-bit
mode for absolute addresses, ~RM is the size of the immediate operand
--
1.8.5.3
- [Qemu-devel] [PULL 03/15] tcg/optimize: fix known-zero bits for right shift ops, (continued)
- [Qemu-devel] [PULL 03/15] tcg/optimize: fix known-zero bits for right shift ops, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 04/15] tcg/optimize: fix known-zero bits optimization, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 05/15] tcg/optimize: improve known-zero bits for 32-bit ops, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 06/15] tcg/optimize: add known-zero bits compute for load ops, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 07/15] tcg/optimize: Handle known-zeros masks for ANDC, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 08/15] tcg/optimize: Simply some logical ops to NOT, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 09/15] tcg/optimize: Optmize ANDC X, Y, Y to MOV X, 0, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 10/15] tcg/optimize: Add more identity simplifications, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 11/15] disas/i386: Disassemble ANDN/SHLX/SHRX/SHAX, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 12/15] tcg/i386: Move TCG_CT_CONST_* to tcg-target.c, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 13/15] tcg/i386: Add tcg_out_vex_modrm,
Richard Henderson <=
- [Qemu-devel] [PULL 15/15] tcg/i386: Use SHLX/SHRX/SARX instructions, Richard Henderson, 2014/02/17
- [Qemu-devel] [PULL 14/15] tcg/i386: Use ANDN instruction, Richard Henderson, 2014/02/17
- Re: [Qemu-devel] [PULL 00/15] tcg updates, Kevin Wolf, 2014/02/19
- Re: [Qemu-devel] [PULL 00/15] tcg updates, Peter Maydell, 2014/02/20