Re: [Qemu-devel] [PATCH 4/7] allwinner-a10-pit: use level triggered interrupts

[Beniamino Galvani]

On Tue, Feb 18, 2014 at 11:51:42AM +0800, Li Guang wrote:
> Beniamino Galvani wrote:
> >Converts the interrupt generation logic to the use of level triggered
> >interrupts.
> 
> any real difference, or block something?

This is a consequence of the change to the implementation of pending
register of the interrupt controller in patch 2.

Beniamino

> 
> >Signed-off-by: Beniamino Galvani<address@hidden>
> >---
> >  hw/timer/allwinner-a10-pit.c |   13 ++++++++++++-
> >  1 file changed, 12 insertions(+), 1 deletion(-)
> >
> >diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c
> >index 3e1c183..4723b25 100644
> >--- a/hw/timer/allwinner-a10-pit.c
> >+++ b/hw/timer/allwinner-a10-pit.c
> >@@ -24,6 +24,15 @@ typedef struct TimerContext {
> >      int index;
> >  } TimerContext;
> >
> >+static void a10_pit_update_irq(AwA10PITState *s)
> >+{
> >+    int i;
> >+
> >+    for (i = 0; i<  AW_A10_PIT_TIMER_NR; i++) {
> >+        qemu_set_irq(s->irq[i], s->irq_status&  s->irq_enable&  (1<<  i));
> >+    }
> >+}
> >+
> >  static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
> >  {
> >      AwA10PITState *s = AW_A10_PIT(opaque);
> >@@ -79,9 +88,11 @@ static void a10_pit_write(void *opaque, hwaddr offset, 
> >uint64_t value,
> >      switch (offset) {
> >      case AW_A10_PIT_TIMER_IRQ_EN:
> >          s->irq_enable = value;
> >+        a10_pit_update_irq(s);
> >          break;
> >      case AW_A10_PIT_TIMER_IRQ_ST:
> >          s->irq_status&= ~value;
> >+        a10_pit_update_irq(s);
> >          break;
> >      case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
> >          index = offset&  0xf0;
> >@@ -208,7 +219,7 @@ static void a10_pit_timer_cb(void *opaque)
> >              ptimer_stop(s->timer[i]);
> >              s->control[i]&= ~AW_A10_PIT_TIMER_EN;
> >          }
> >-        qemu_irq_pulse(s->irq[i]);
> >+        a10_pit_update_irq(s);
> >      }
> >  }
> >
>